arm/mach-pxa/trizeps4.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /************************************************************************
0003  * Include file for TRIZEPS4 SoM and ConXS eval-board
0004  * Copyright (c) Jürgen Schindele
0005  * 2006
0006  ************************************************************************/
0007
0008 /*
0009  * Includes/Defines
0010  */
0011 #ifndef _TRIPEPS4_H_
0012 #define _TRIPEPS4_H_
0013
0014 #include "addr-map.h"
0015 #include "irqs.h" /* PXA_GPIO_TO_IRQ */
0016
0017 /* physical memory regions */
0018 #define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS)  /* Flash region */
0019 #define TRIZEPS4_DISK_PHYS  (PXA_CS1_PHYS)  /* Disk On Chip region */
0020 #define TRIZEPS4_ETH_PHYS   (PXA_CS2_PHYS)  /* Ethernet DM9000 region */
0021 #define TRIZEPS4_PIC_PHYS   (PXA_CS3_PHYS)  /* Logic chip on ConXS-Board */
0022 #define TRIZEPS4_SDRAM_BASE 0xa0000000      /* SDRAM region */
0023
0024                 /* Logic on ConXS-board CSFR register*/
0025 #define TRIZEPS4_CFSR_PHYS  (PXA_CS3_PHYS)
0026                 /* Logic on ConXS-board BOCR register*/
0027 #define TRIZEPS4_BOCR_PHYS  (PXA_CS3_PHYS+0x02000000)
0028                 /* Logic on ConXS-board IRCR register*/
0029 #define TRIZEPS4_IRCR_PHYS  (PXA_CS3_PHYS+0x02400000)
0030                 /* Logic on ConXS-board UPSR register*/
0031 #define TRIZEPS4_UPSR_PHYS  (PXA_CS3_PHYS+0x02800000)
0032                 /* Logic on ConXS-board DICR register*/
0033 #define TRIZEPS4_DICR_PHYS  (PXA_CS3_PHYS+0x03800000)
0034
0035 /* virtual memory regions */
0036 #define TRIZEPS4_DISK_VIRT  0xF0000000  /* Disk On Chip region */
0037
0038 #define TRIZEPS4_PIC_VIRT   0xF0100000  /* not used */
0039 #define TRIZEPS4_CFSR_VIRT  0xF0100000
0040 #define TRIZEPS4_BOCR_VIRT  0xF0200000
0041 #define TRIZEPS4_DICR_VIRT  0xF0300000
0042 #define TRIZEPS4_IRCR_VIRT  0xF0400000
0043 #define TRIZEPS4_UPSR_VIRT  0xF0500000
0044
0045 /* size of flash */
0046 #define TRIZEPS4_FLASH_SIZE 0x02000000  /* Flash size 32 MB */
0047
0048 /* Ethernet Controller Davicom DM9000 */
0049 #define GPIO_DM9000     101
0050 #define TRIZEPS4_ETH_IRQ    PXA_GPIO_TO_IRQ(GPIO_DM9000)
0051
0052 /* UCB1400 audio / TS-controller */
0053 #define GPIO_UCB1400        1
0054 #define TRIZEPS4_UCB1400_IRQ    PXA_GPIO_TO_IRQ(GPIO_UCB1400)
0055
0056 /* PCMCIA socket Compact Flash */
0057 #define GPIO_PCD        11      /* PCMCIA Card Detect */
0058 #define TRIZEPS4_CD_IRQ     PXA_GPIO_TO_IRQ(GPIO_PCD)
0059 #define GPIO_PRDY       13      /* READY / nINT */
0060 #define TRIZEPS4_READY_NINT PXA_GPIO_TO_IRQ(GPIO_PRDY)
0061
0062 /* MMC socket */
0063 #define GPIO_MMC_DET        12
0064 #define TRIZEPS4_MMC_IRQ    PXA_GPIO_TO_IRQ(GPIO_MMC_DET)
0065
0066 /* DOC NAND chip */
0067 #define GPIO_DOC_LOCK           94
0068 #define GPIO_DOC_IRQ            93
0069 #define TRIZEPS4_DOC_IRQ        PXA_GPIO_TO_IRQ(GPIO_DOC_IRQ)
0070
0071 /* SPI interface */
0072 #define GPIO_SPI                53
0073 #define TRIZEPS4_SPI_IRQ        PXA_GPIO_TO_IRQ(GPIO_SPI)
0074
0075 /* LEDS using tx2 / rx2 */
0076 #define GPIO_SYS_BUSY_LED   46
0077 #define GPIO_HEARTBEAT_LED  47
0078
0079 /* Off-module PIC on ConXS board */
0080 #define GPIO_PIC        0
0081 #define TRIZEPS4_PIC_IRQ    PXA_GPIO_TO_IRQ(GPIO_PIC)
0082
0083 #ifdef CONFIG_MACH_TRIZEPS_CONXS
0084 /* for CONXS base board define these registers */
0085 #define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
0086 #define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
0087
0088 #define BCR_P2V(x)  ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
0089 #define BCR_V2P(x)  ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
0090
0091 #define DCR_P2V(x)  ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
0092 #define DCR_V2P(x)  ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
0093
0094 #define IRCR_P2V(x) ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT)
0095 #define IRCR_V2P(x) ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS)
0096
0097 #ifndef __ASSEMBLY__
0098 static inline unsigned short CFSR_readw(void)
0099 {
0100     /* [Compact Flash Status Register] is read only */
0101     return *((unsigned short *)CFSR_P2V(0x0C000000));
0102 }
0103 static inline void BCR_writew(unsigned short value)
0104 {
0105     /* [Board Control Regsiter] is write only */
0106     *((unsigned short *)BCR_P2V(0x0E000000)) = value;
0107 }
0108 static inline void DCR_writew(unsigned short value)
0109 {
0110     /* [Display Control Register] is write only */
0111     *((unsigned short *)DCR_P2V(0x0E000000)) = value;
0112 }
0113 static inline void IRCR_writew(unsigned short value)
0114 {
0115     /* [InfraRed data Control Register] is write only */
0116     *((unsigned short *)IRCR_P2V(0x0E000000)) = value;
0117 }
0118 #else
0119 #define ConXS_CFSR      CFSR_P2V(0x0C000000)
0120 #define ConXS_BCR       BCR_P2V(0x0E000000)
0121 #define ConXS_DCR       DCR_P2V(0x0F800000)
0122 #define ConXS_IRCR      IRCR_P2V(0x0F800000)
0123 #endif
0124 #else
0125 /* for whatever baseboard define function registers */
0126 static inline unsigned short CFSR_readw(void)
0127 {
0128     return 0;
0129 }
0130 static inline void BCR_writew(unsigned short value)
0131 {
0132     ;
0133 }
0134 static inline void DCR_writew(unsigned short value)
0135 {
0136     ;
0137 }
0138 static inline void IRCR_writew(unsigned short value)
0139 {
0140     ;
0141 }
0142 #endif  /* CONFIG_MACH_TRIZEPS_CONXS */
0143
0144 #define ConXS_CFSR_BVD_MASK 0x0003
0145 #define ConXS_CFSR_BVD1     (1 << 0)
0146 #define ConXS_CFSR_BVD2     (1 << 1)
0147 #define ConXS_CFSR_VS_MASK  0x000C
0148 #define ConXS_CFSR_VS1      (1 << 2)
0149 #define ConXS_CFSR_VS2      (1 << 3)
0150 #define ConXS_CFSR_VS_5V    (0x3 << 2)
0151 #define ConXS_CFSR_VS_3V3   0x0
0152
0153 #define ConXS_BCR_S0_POW_EN0    (1 << 0)
0154 #define ConXS_BCR_S0_POW_EN1    (1 << 1)
0155 #define ConXS_BCR_L_DISP    (1 << 4)
0156 #define ConXS_BCR_CF_BUF_EN (1 << 5)
0157 #define ConXS_BCR_CF_RESET  (1 << 7)
0158 #define ConXS_BCR_S0_VCC_3V3    0x1
0159 #define ConXS_BCR_S0_VCC_5V0    0x2
0160 #define ConXS_BCR_S0_VPP_12V    0x4
0161 #define ConXS_BCR_S0_VPP_3V3    0x8
0162
0163 #define ConXS_IRCR_MODE     (1 << 0)
0164 #define ConXS_IRCR_SD       (1 << 1)
0165
0166 #endif /* _TRIPEPS4_H_ */