arm/mach-pxa/standby.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * PXA27x standby mode
0004  *
0005  * Author: David Burrage
0006  *
0007  * 2005 (c) MontaVista Software, Inc.
0008  */
0009
0010 #include <linux/linkage.h>
0011 #include <asm/assembler.h>
0012
0013 #include "pxa2xx-regs.h"
0014
0015         .text
0016
0017 #ifdef CONFIG_PXA27x
0018 ENTRY(pxa_cpu_standby)
0019     ldr r0, =PSSR
0020     mov r1, #(PSSR_PH | PSSR_STS)
0021     mov r2, #PWRMODE_STANDBY
0022     mov r3, #UNCACHED_PHYS_0    @ Read mem context in.
0023     ldr ip, [r3]
0024     b   1f
0025
0026     .align  5
0027 1:  mcr p14, 0, r2, c7, c0, 0   @ put the system into Standby
0028     str r1, [r0]        @ make sure PSSR_PH/STS are clear
0029     ret lr
0030
0031 #endif
0032
0033 #ifdef CONFIG_PXA3xx
0034
0035 #define PXA3_MDCNFG     0x0000
0036 #define PXA3_MDCNFG_DMCEN   (1 << 30)
0037 #define PXA3_DDR_HCAL       0x0060
0038 #define PXA3_DDR_HCAL_HCRNG 0x1f
0039 #define PXA3_DDR_HCAL_HCPROG    (1 << 28)
0040 #define PXA3_DDR_HCAL_HCEN  (1 << 31)
0041 #define PXA3_DMCIER     0x0070
0042 #define PXA3_DMCIER_EDLP    (1 << 29)
0043 #define PXA3_DMCISR     0x0078
0044 #define PXA3_RCOMP      0x0100
0045 #define PXA3_RCOMP_SWEVAL   (1 << 31)
0046
0047 ENTRY(pm_enter_standby_start)
0048     mov r1, #0xf6000000         @ DMEMC_REG_BASE (PXA3_MDCNFG)
0049     add r1, r1, #0x00100000
0050
0051     /*
0052      * Preload the TLB entry for accessing the dynamic memory
0053      * controller registers.  Note that page table lookups will
0054      * fail until the dynamic memory controller has been
0055      * reinitialised - and that includes MMU page table walks.
0056      * This also means that only the dynamic memory controller
0057      * can be reliably accessed in the code following standby.
0058      */
0059     ldr r2, [r1]            @ Dummy read PXA3_MDCNFG
0060
0061     mcr p14, 0, r0, c7, c0, 0
0062     .rept   8
0063     nop
0064     .endr
0065
0066     ldr r0, [r1, #PXA3_DDR_HCAL]    @ Clear (and wait for) HCEN
0067     bic r0, r0, #PXA3_DDR_HCAL_HCEN
0068     str r0, [r1, #PXA3_DDR_HCAL]
0069 1:  ldr r0, [r1, #PXA3_DDR_HCAL]
0070     tst r0, #PXA3_DDR_HCAL_HCEN
0071     bne 1b
0072
0073     ldr r0, [r1, #PXA3_RCOMP]       @ Initiate RCOMP
0074     orr r0, r0, #PXA3_RCOMP_SWEVAL
0075     str r0, [r1, #PXA3_RCOMP]
0076
0077     mov r0, #~0             @ Clear interrupts
0078     str r0, [r1, #PXA3_DMCISR]
0079
0080     ldr r0, [r1, #PXA3_DMCIER]      @ set DMIER[EDLP]
0081     orr r0, r0, #PXA3_DMCIER_EDLP
0082     str r0, [r1, #PXA3_DMCIER]
0083
0084     ldr r0, [r1, #PXA3_DDR_HCAL]    @ clear HCRNG, set HCPROG, HCEN
0085     bic r0, r0, #PXA3_DDR_HCAL_HCRNG
0086     orr r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG
0087     str r0, [r1, #PXA3_DDR_HCAL]
0088
0089 1:  ldr r0, [r1, #PXA3_DMCISR]
0090     tst r0, #PXA3_DMCIER_EDLP
0091     beq 1b
0092
0093     ldr r0, [r1, #PXA3_MDCNFG]      @ set PXA3_MDCNFG[DMCEN]
0094     orr r0, r0, #PXA3_MDCNFG_DMCEN
0095     str r0, [r1, #PXA3_MDCNFG]
0096 1:  ldr r0, [r1, #PXA3_MDCNFG]
0097     tst r0, #PXA3_MDCNFG_DMCEN
0098     beq 1b
0099
0100     ldr r0, [r1, #PXA3_DDR_HCAL]    @ set PXA3_DDR_HCAL[HCRNG]
0101     orr r0, r0, #2 @ HCRNG
0102     str r0, [r1, #PXA3_DDR_HCAL]
0103
0104     ldr r0, [r1, #PXA3_DMCIER]      @ Clear the interrupt
0105     bic r0, r0, #0x20000000
0106     str r0, [r1, #PXA3_DMCIER]
0107
0108     ret lr
0109 ENTRY(pm_enter_standby_end)
0110
0111 #endif