arm/mach-pxa/smemc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Static memory controller register definitions for PXA CPUs
0004  *
0005  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
0006  */
0007
0008 #ifndef __SMEMC_REGS_H
0009 #define __SMEMC_REGS_H
0010
0011 #define PXA2XX_SMEMC_BASE   0x48000000
0012 #define PXA3XX_SMEMC_BASE   0x4a000000
0013 #define SMEMC_VIRT      IOMEM(0xf6000000)
0014
0015 #define MDCNFG      (SMEMC_VIRT + 0x00)  /* SDRAM Configuration Register 0 */
0016 #define MDREFR      (SMEMC_VIRT + 0x04)  /* SDRAM Refresh Control Register */
0017 #define MSC0        (SMEMC_VIRT + 0x08)  /* Static Memory Control Register 0 */
0018 #define MSC1        (SMEMC_VIRT + 0x0C)  /* Static Memory Control Register 1 */
0019 #define MSC2        (SMEMC_VIRT + 0x10)  /* Static Memory Control Register 2 */
0020 #define MECR        (SMEMC_VIRT + 0x14)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
0021 #define SXLCR       (SMEMC_VIRT + 0x18)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
0022 #define SXCNFG      (SMEMC_VIRT + 0x1C)  /* Synchronous Static Memory Control Register */
0023 #define SXMRS       (SMEMC_VIRT + 0x24)  /* MRS value to be written to Synchronous Flash or SMROM */
0024 #define MCMEM0      (SMEMC_VIRT + 0x28)  /* Card interface Common Memory Space Socket 0 Timing */
0025 #define MCMEM1      (SMEMC_VIRT + 0x2C)  /* Card interface Common Memory Space Socket 1 Timing */
0026 #define MCATT0      (SMEMC_VIRT + 0x30)  /* Card interface Attribute Space Socket 0 Timing Configuration */
0027 #define MCATT1      (SMEMC_VIRT + 0x34)  /* Card interface Attribute Space Socket 1 Timing Configuration */
0028 #define MCIO0       (SMEMC_VIRT + 0x38)  /* Card interface I/O Space Socket 0 Timing Configuration */
0029 #define MCIO1       (SMEMC_VIRT + 0x3C)  /* Card interface I/O Space Socket 1 Timing Configuration */
0030 #define MDMRS       (SMEMC_VIRT + 0x40)  /* MRS value to be written to SDRAM */
0031 #define BOOT_DEF    (SMEMC_VIRT + 0x44)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
0032 #define MEMCLKCFG   (SMEMC_VIRT + 0x68)  /* Clock Configuration */
0033 #define CSADRCFG0   (SMEMC_VIRT + 0x80)  /* Address Configuration Register for CS0 */
0034 #define CSADRCFG1   (SMEMC_VIRT + 0x84)  /* Address Configuration Register for CS1 */
0035 #define CSADRCFG2   (SMEMC_VIRT + 0x88)  /* Address Configuration Register for CS2 */
0036 #define CSADRCFG3   (SMEMC_VIRT + 0x8C)  /* Address Configuration Register for CS3 */
0037 #define CSMSADRCFG  (SMEMC_VIRT + 0xA0)  /* Chip Select Configuration Register */
0038
0039 /*
0040  * More handy macros for PCMCIA
0041  *
0042  * Arg is socket number
0043  */
0044 #define MCMEM(s)    (SMEMC_VIRT + 0x28 + ((s)<<2))  /* Card interface Common Memory Space Socket s Timing */
0045 #define MCATT(s)    (SMEMC_VIRT + 0x30 + ((s)<<2))  /* Card interface Attribute Space Socket s Timing Configuration */
0046 #define MCIO(s)     (SMEMC_VIRT + 0x38 + ((s)<<2))  /* Card interface I/O Space Socket s Timing Configuration */
0047
0048 /* MECR register defines */
0049 #define MECR_NOS    (1 << 0)    /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
0050 #define MECR_CIT    (1 << 1)    /* Card Is There: 0 -> no card, 1 -> card inserted */
0051
0052 #define MDCNFG_DE0  (1 << 0)    /* SDRAM Bank 0 Enable */
0053 #define MDCNFG_DE1  (1 << 1)    /* SDRAM Bank 1 Enable */
0054 #define MDCNFG_DE2  (1 << 16)   /* SDRAM Bank 2 Enable */
0055 #define MDCNFG_DE3  (1 << 17)   /* SDRAM Bank 3 Enable */
0056
0057 #define MDREFR_K0DB4    (1 << 29)   /* SDCLK0 Divide by 4 Control/Status */
0058 #define MDREFR_K2FREE   (1 << 25)   /* SDRAM Free-Running Control */
0059 #define MDREFR_K1FREE   (1 << 24)   /* SDRAM Free-Running Control */
0060 #define MDREFR_K0FREE   (1 << 23)   /* SDRAM Free-Running Control */
0061 #define MDREFR_SLFRSH   (1 << 22)   /* SDRAM Self-Refresh Control/Status */
0062 #define MDREFR_APD  (1 << 20)   /* SDRAM/SSRAM Auto-Power-Down Enable */
0063 #define MDREFR_K2DB2    (1 << 19)   /* SDCLK2 Divide by 2 Control/Status */
0064 #define MDREFR_K2RUN    (1 << 18)   /* SDCLK2 Run Control/Status */
0065 #define MDREFR_K1DB2    (1 << 17)   /* SDCLK1 Divide by 2 Control/Status */
0066 #define MDREFR_K1RUN    (1 << 16)   /* SDCLK1 Run Control/Status */
0067 #define MDREFR_E1PIN    (1 << 15)   /* SDCKE1 Level Control/Status */
0068 #define MDREFR_K0DB2    (1 << 14)   /* SDCLK0 Divide by 2 Control/Status */
0069 #define MDREFR_K0RUN    (1 << 13)   /* SDCLK0 Run Control/Status */
0070 #define MDREFR_E0PIN    (1 << 12)   /* SDCKE0 Level Control/Status */
0071
0072 #endif