arm/mach-pxa/smemc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Static Memory Controller
0004  */
0005
0006 #include <linux/module.h>
0007 #include <linux/kernel.h>
0008 #include <linux/init.h>
0009 #include <linux/io.h>
0010 #include <linux/syscore_ops.h>
0011 #include <linux/soc/pxa/cpu.h>
0012
0013 #include "smemc.h"
0014 #include <linux/soc/pxa/smemc.h>
0015
0016 #ifdef CONFIG_PM
0017 static unsigned long msc[2];
0018 static unsigned long sxcnfg, memclkcfg;
0019 static unsigned long csadrcfg[4];
0020
0021 static int pxa3xx_smemc_suspend(void)
0022 {
0023     msc[0] = __raw_readl(MSC0);
0024     msc[1] = __raw_readl(MSC1);
0025     sxcnfg = __raw_readl(SXCNFG);
0026     memclkcfg = __raw_readl(MEMCLKCFG);
0027     csadrcfg[0] = __raw_readl(CSADRCFG0);
0028     csadrcfg[1] = __raw_readl(CSADRCFG1);
0029     csadrcfg[2] = __raw_readl(CSADRCFG2);
0030     csadrcfg[3] = __raw_readl(CSADRCFG3);
0031
0032     return 0;
0033 }
0034
0035 static void pxa3xx_smemc_resume(void)
0036 {
0037     __raw_writel(msc[0], MSC0);
0038     __raw_writel(msc[1], MSC1);
0039     __raw_writel(sxcnfg, SXCNFG);
0040     __raw_writel(memclkcfg, MEMCLKCFG);
0041     __raw_writel(csadrcfg[0], CSADRCFG0);
0042     __raw_writel(csadrcfg[1], CSADRCFG1);
0043     __raw_writel(csadrcfg[2], CSADRCFG2);
0044     __raw_writel(csadrcfg[3], CSADRCFG3);
0045     /* CSMSADRCFG wakes up in its default state (0), so we need to set it */
0046     __raw_writel(0x2, CSMSADRCFG);
0047 }
0048
0049 static struct syscore_ops smemc_syscore_ops = {
0050     .suspend    = pxa3xx_smemc_suspend,
0051     .resume     = pxa3xx_smemc_resume,
0052 };
0053
0054 static int __init smemc_init(void)
0055 {
0056     if (cpu_is_pxa3xx()) {
0057         /*
0058          * The only documentation we have on the
0059          * Chip Select Configuration Register (CSMSADRCFG) is that
0060          * it must be programmed to 0x2.
0061          * Moreover, in the bit definitions, the second bit
0062          * (CSMSADRCFG[1]) is called "SETALWAYS".
0063          * Other bits are reserved in this register.
0064          */
0065         __raw_writel(0x2, CSMSADRCFG);
0066
0067         register_syscore_ops(&smemc_syscore_ops);
0068     }
0069
0070     return 0;
0071 }
0072 subsys_initcall(smemc_init);
0073 #endif
0074
0075 static const unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
0076 unsigned int pxa3xx_smemc_get_memclkdiv(void)
0077 {
0078     unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
0079
0080     return  df_clkdiv[(memclkcfg >> 16) & 0x3];
0081 }