arm/mach-pxa/sleep.S

0001 /*
0002  * Low-level PXA250/210 sleep/wakeUp support
0003  *
0004  * Initial SA1110 code:
0005  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
0006  *
0007  * Adapted for PXA by Nicolas Pitre:
0008  * Copyright (c) 2002 Monta Vista Software, Inc.
0009  *
0010  * This program is free software; you can redistribute it and/or
0011  * modify it under the terms of the GNU General Public License.
0012  */
0013
0014 #include <linux/linkage.h>
0015 #include <asm/assembler.h>
0016 #include "smemc.h"
0017 #include "pxa2xx-regs.h"
0018
0019 #define MDREFR_KDIV 0x200a4000  // all banks
0020 #define CCCR_SLEEP  0x00000107  // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
0021 #define CCCR_N_MASK     0x00000380
0022 #define CCCR_M_MASK     0x00000060
0023 #define CCCR_L_MASK     0x0000001f
0024         .text
0025
0026 #ifdef CONFIG_PXA3xx
0027 /*
0028  * pxa3xx_finish_suspend() - forces CPU into sleep state (S2D3C4)
0029  */
0030 ENTRY(pxa3xx_finish_suspend)
0031     mov r0, #0x06       @ S2D3C4 mode
0032     mcr p14, 0, r0, c7, c0, 0   @ enter sleep
0033
0034 20: b   20b         @ waiting for sleep
0035 #endif /* CONFIG_PXA3xx */
0036
0037 #ifdef CONFIG_PXA27x
0038 /*
0039  * pxa27x_finish_suspend()
0040  *
0041  * Forces CPU into sleep state.
0042  *
0043  * r0 = value for PWRMODE M field for desired sleep state
0044  */
0045 ENTRY(pxa27x_finish_suspend)
0046     @ Put the processor to sleep
0047     @ (also workaround for sighting 28071)
0048
0049     @ prepare value for sleep mode
0050     mov r1, r0              @ sleep mode
0051
0052     @ prepare pointer to physical address 0 (virtual mapping in generic.c)
0053     mov r2, #UNCACHED_PHYS_0
0054
0055     @ prepare SDRAM refresh settings
0056     ldr r4, =MDREFR
0057     ldr r5, [r4]
0058
0059     @ enable SDRAM self-refresh mode
0060     orr r5, r5, #MDREFR_SLFRSH
0061
0062     @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
0063     ldr r6, =MDREFR_KDIV
0064     orr r5, r5, r6
0065
0066     @ Intel PXA270 Specification Update notes problems sleeping
0067     @ with core operating above 91 MHz
0068     @ (see Errata 50, ...processor does not exit from sleep...)
0069
0070     ldr r6, =CCCR
0071     ldr r8, [r6]        @ keep original value for resume
0072
0073     ldr r7, =CCCR_SLEEP     @ prepare CCCR sleep value
0074     mov r0, #0x2        @ prepare value for CLKCFG
0075
0076     @ align execution to a cache line
0077     b   pxa_cpu_do_suspend
0078 #endif
0079
0080 #ifdef CONFIG_PXA25x
0081 /*
0082  * pxa25x_finish_suspend()
0083  *
0084  * Forces CPU into sleep state.
0085  *
0086  * r0 = value for PWRMODE M field for desired sleep state
0087  */
0088
0089 ENTRY(pxa25x_finish_suspend)
0090     @ prepare value for sleep mode
0091     mov r1, r0              @ sleep mode
0092
0093     @ prepare pointer to physical address 0 (virtual mapping in generic.c)
0094     mov r2, #UNCACHED_PHYS_0
0095
0096     @ prepare SDRAM refresh settings
0097     ldr r4, =MDREFR
0098     ldr r5, [r4]
0099
0100     @ enable SDRAM self-refresh mode
0101     orr r5, r5, #MDREFR_SLFRSH
0102
0103     @ Intel PXA255 Specification Update notes problems
0104     @ about suspending with PXBus operating above 133MHz
0105     @ (see Errata 31, GPIO output signals, ... unpredictable in sleep
0106     @
0107     @ We keep the change-down close to the actual suspend on SDRAM
0108     @ as possible to eliminate messing about with the refresh clock
0109     @ as the system will restore with the original speed settings
0110     @
0111     @ Ben Dooks, 13-Sep-2004
0112
0113     ldr r6, =CCCR
0114     ldr r8, [r6]        @ keep original value for resume
0115
0116     @ ensure x1 for run and turbo mode with memory clock
0117     bic r7, r8, #CCCR_M_MASK | CCCR_N_MASK
0118     orr r7, r7, #(1<<5) | (2<<7)
0119
0120     @ check that the memory frequency is within limits
0121     and r14, r7, #CCCR_L_MASK
0122     teq r14, #1
0123     bicne   r7, r7, #CCCR_L_MASK
0124     orrne   r7, r7, #1          @@ 99.53MHz
0125
0126     @ get ready for the change
0127
0128     @ note, turbo is not preserved over sleep so there is no
0129     @ point in preserving it here. we save it on the stack with the
0130     @ other CP registers instead.
0131     mov r0, #0
0132     mcr p14, 0, r0, c6, c0, 0
0133     orr r0, r0, #2          @ initiate change bit
0134     b   pxa_cpu_do_suspend
0135 #endif
0136
0137     .ltorg
0138     .align  5
0139 pxa_cpu_do_suspend:
0140
0141     @ All needed values are now in registers.
0142     @ These last instructions should be in cache
0143
0144     @ initiate the frequency change...
0145     str r7, [r6]
0146     mcr p14, 0, r0, c6, c0, 0
0147
0148     @ restore the original cpu speed value for resume
0149     str r8, [r6]
0150
0151     @ need 6 13-MHz cycles before changing PWRMODE
0152     @ just set frequency to 91-MHz... 6*91/13 = 42
0153
0154     mov r0, #42
0155 10: subs    r0, r0, #1
0156     bne 10b
0157
0158     @ Do not reorder...
0159     @ Intel PXA270 Specification Update notes problems performing
0160     @ external accesses after SDRAM is put in self-refresh mode
0161     @ (see Errata 38 ...hangs when entering self-refresh mode)
0162
0163     @ force address lines low by reading at physical address 0
0164     ldr r3, [r2]
0165
0166     @ put SDRAM into self-refresh
0167     str r5, [r4]
0168
0169     @ enter sleep mode
0170     mcr p14, 0, r1, c7, c0, 0       @ PWRMODE
0171
0172 20: b   20b             @ loop waiting for sleep