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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/arch/arm/mach-pxa/saar.c
0004  *
0005  *  Support for the Marvell PXA930 Handheld Platform (aka SAAR)
0006  *
0007  *  Copyright (C) 2007-2008 Marvell International Ltd.
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/kernel.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/init.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/clk.h>
0016 #include <linux/gpio.h>
0017 #include <linux/delay.h>
0018 #include <linux/fb.h>
0019 #include <linux/i2c.h>
0020 #include <linux/platform_data/i2c-pxa.h>
0021 #include <linux/smc91x.h>
0022 #include <linux/mfd/da903x.h>
0023 #include <linux/mtd/mtd.h>
0024 #include <linux/mtd/partitions.h>
0025 #include <linux/mtd/onenand.h>
0026 
0027 #include <asm/mach-types.h>
0028 #include <asm/mach/arch.h>
0029 #include <asm/mach/flash.h>
0030 
0031 #include "pxa930.h"
0032 #include <linux/platform_data/video-pxafb.h>
0033 
0034 #include "devices.h"
0035 #include "generic.h"
0036 
0037 #define GPIO_LCD_RESET      (16)
0038 
0039 /* SAAR MFP configurations */
0040 static mfp_cfg_t saar_mfp_cfg[] __initdata = {
0041     /* LCD */
0042     GPIO23_LCD_DD0,
0043     GPIO24_LCD_DD1,
0044     GPIO25_LCD_DD2,
0045     GPIO26_LCD_DD3,
0046     GPIO27_LCD_DD4,
0047     GPIO28_LCD_DD5,
0048     GPIO29_LCD_DD6,
0049     GPIO44_LCD_DD7,
0050     GPIO21_LCD_CS,
0051     GPIO22_LCD_VSYNC,
0052     GPIO17_LCD_FCLK_RD,
0053     GPIO18_LCD_LCLK_A0,
0054     GPIO19_LCD_PCLK_WR,
0055     GPIO16_GPIO, /* LCD reset */
0056 
0057     /* Ethernet */
0058     DF_nCS1_nCS3,
0059     GPIO97_GPIO,
0060 
0061     /* DFI */
0062     DF_INT_RnB_ND_INT_RnB,
0063     DF_nRE_nOE_ND_nRE,
0064     DF_nWE_ND_nWE,
0065     DF_CLE_nOE_ND_CLE,
0066     DF_nADV1_ALE_ND_ALE,
0067     DF_nADV2_ALE_nCS3,
0068     DF_nCS0_ND_nCS0,
0069     DF_IO0_ND_IO0,
0070     DF_IO1_ND_IO1,
0071     DF_IO2_ND_IO2,
0072     DF_IO3_ND_IO3,
0073     DF_IO4_ND_IO4,
0074     DF_IO5_ND_IO5,
0075     DF_IO6_ND_IO6,
0076     DF_IO7_ND_IO7,
0077     DF_IO8_ND_IO8,
0078     DF_IO9_ND_IO9,
0079     DF_IO10_ND_IO10,
0080     DF_IO11_ND_IO11,
0081     DF_IO12_ND_IO12,
0082     DF_IO13_ND_IO13,
0083     DF_IO14_ND_IO14,
0084     DF_IO15_ND_IO15,
0085 };
0086 
0087 #define SAAR_ETH_PHYS   (0x14000000)
0088 
0089 static struct resource smc91x_resources[] = {
0090     [0] = {
0091         .start  = (SAAR_ETH_PHYS + 0x300),
0092         .end    = (SAAR_ETH_PHYS + 0xfffff),
0093         .flags  = IORESOURCE_MEM,
0094     },
0095     [1] = {
0096         .start  = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)),
0097         .end    = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)),
0098         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
0099     }
0100 };
0101 
0102 static struct smc91x_platdata saar_smc91x_info = {
0103     .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_USE_DMA,
0104 };
0105 
0106 static struct platform_device smc91x_device = {
0107     .name       = "smc91x",
0108     .id     = 0,
0109     .num_resources  = ARRAY_SIZE(smc91x_resources),
0110     .resource   = smc91x_resources,
0111     .dev        = {
0112         .platform_data = &saar_smc91x_info,
0113     },
0114 };
0115 
0116 #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
0117 static uint16_t lcd_power_on[] = {
0118     /* single frame */
0119     SMART_CMD_NOOP,
0120     SMART_CMD(0x00),
0121     SMART_DELAY(0),
0122 
0123     SMART_CMD_NOOP,
0124     SMART_CMD(0x00),
0125     SMART_DELAY(0),
0126 
0127     SMART_CMD_NOOP,
0128     SMART_CMD(0x00),
0129     SMART_DELAY(0),
0130 
0131     SMART_CMD_NOOP,
0132     SMART_CMD(0x00),
0133     SMART_DELAY(10),
0134 
0135     /* calibration control */
0136     SMART_CMD(0x00),
0137     SMART_CMD(0xA4),
0138     SMART_DAT(0x80),
0139     SMART_DAT(0x01),
0140     SMART_DELAY(150),
0141 
0142     /*Power-On Init sequence*/
0143     SMART_CMD(0x00),    /* output ctrl */
0144     SMART_CMD(0x01),
0145     SMART_DAT(0x01),
0146     SMART_DAT(0x00),
0147     SMART_CMD(0x00),    /* wave ctrl */
0148     SMART_CMD(0x02),
0149     SMART_DAT(0x07),
0150     SMART_DAT(0x00),
0151     SMART_CMD(0x00),
0152     SMART_CMD(0x03),    /* entry mode */
0153     SMART_DAT(0xD0),
0154     SMART_DAT(0x30),
0155     SMART_CMD(0x00),
0156     SMART_CMD(0x08),    /* display ctrl 2 */
0157     SMART_DAT(0x08),
0158     SMART_DAT(0x08),
0159     SMART_CMD(0x00),
0160     SMART_CMD(0x09),    /* display ctrl 3 */
0161     SMART_DAT(0x04),
0162     SMART_DAT(0x2F),
0163     SMART_CMD(0x00),
0164     SMART_CMD(0x0A),    /* display ctrl 4 */
0165     SMART_DAT(0x00),
0166     SMART_DAT(0x08),
0167     SMART_CMD(0x00),
0168     SMART_CMD(0x0D),    /* Frame Marker position */
0169     SMART_DAT(0x00),
0170     SMART_DAT(0x08),
0171     SMART_CMD(0x00),
0172     SMART_CMD(0x60),    /* Driver output control */
0173     SMART_DAT(0x27),
0174     SMART_DAT(0x00),
0175     SMART_CMD(0x00),
0176     SMART_CMD(0x61),    /* Base image display control */
0177     SMART_DAT(0x00),
0178     SMART_DAT(0x01),
0179     SMART_CMD(0x00),
0180     SMART_CMD(0x30),    /* Y settings 30h-3Dh */
0181     SMART_DAT(0x07),
0182     SMART_DAT(0x07),
0183     SMART_CMD(0x00),
0184     SMART_CMD(0x31),
0185     SMART_DAT(0x00),
0186     SMART_DAT(0x07),
0187     SMART_CMD(0x00),
0188     SMART_CMD(0x32),    /* Timing(3), ASW HOLD=0.5CLK */
0189     SMART_DAT(0x04),
0190     SMART_DAT(0x00),
0191     SMART_CMD(0x00),
0192     SMART_CMD(0x33),    /* Timing(4), CKV ST=0CLK, CKV ED=1CLK */
0193     SMART_DAT(0x03),
0194     SMART_DAT(0x03),
0195     SMART_CMD(0x00),
0196     SMART_CMD(0x34),
0197     SMART_DAT(0x00),
0198     SMART_DAT(0x00),
0199     SMART_CMD(0x00),
0200     SMART_CMD(0x35),
0201     SMART_DAT(0x02),
0202     SMART_DAT(0x05),
0203     SMART_CMD(0x00),
0204     SMART_CMD(0x36),
0205     SMART_DAT(0x1F),
0206     SMART_DAT(0x1F),
0207     SMART_CMD(0x00),
0208     SMART_CMD(0x37),
0209     SMART_DAT(0x07),
0210     SMART_DAT(0x07),
0211     SMART_CMD(0x00),
0212     SMART_CMD(0x38),
0213     SMART_DAT(0x00),
0214     SMART_DAT(0x07),
0215     SMART_CMD(0x00),
0216     SMART_CMD(0x39),
0217     SMART_DAT(0x04),
0218     SMART_DAT(0x00),
0219     SMART_CMD(0x00),
0220     SMART_CMD(0x3A),
0221     SMART_DAT(0x03),
0222     SMART_DAT(0x03),
0223     SMART_CMD(0x00),
0224     SMART_CMD(0x3B),
0225     SMART_DAT(0x00),
0226     SMART_DAT(0x00),
0227     SMART_CMD(0x00),
0228     SMART_CMD(0x3C),
0229     SMART_DAT(0x02),
0230     SMART_DAT(0x05),
0231     SMART_CMD(0x00),
0232     SMART_CMD(0x3D),
0233     SMART_DAT(0x1F),
0234     SMART_DAT(0x1F),
0235     SMART_CMD(0x00),    /* Display control 1 */
0236     SMART_CMD(0x07),
0237     SMART_DAT(0x00),
0238     SMART_DAT(0x01),
0239     SMART_CMD(0x00),    /* Power control 5 */
0240     SMART_CMD(0x17),
0241     SMART_DAT(0x00),
0242     SMART_DAT(0x01),
0243     SMART_CMD(0x00),    /* Power control 1 */
0244     SMART_CMD(0x10),
0245     SMART_DAT(0x10),
0246     SMART_DAT(0xB0),
0247     SMART_CMD(0x00),    /* Power control 2 */
0248     SMART_CMD(0x11),
0249     SMART_DAT(0x01),
0250     SMART_DAT(0x30),
0251     SMART_CMD(0x00),    /* Power control 3 */
0252     SMART_CMD(0x12),
0253     SMART_DAT(0x01),
0254     SMART_DAT(0x9E),
0255     SMART_CMD(0x00),    /* Power control 4 */
0256     SMART_CMD(0x13),
0257     SMART_DAT(0x17),
0258     SMART_DAT(0x00),
0259     SMART_CMD(0x00),    /* Power control 3 */
0260     SMART_CMD(0x12),
0261     SMART_DAT(0x01),
0262     SMART_DAT(0xBE),
0263     SMART_DELAY(100),
0264 
0265     /* display mode : 240*320 */
0266     SMART_CMD(0x00),    /* RAM address set(H) 0*/
0267     SMART_CMD(0x20),
0268     SMART_DAT(0x00),
0269     SMART_DAT(0x00),
0270     SMART_CMD(0x00),    /* RAM address set(V)   4*/
0271     SMART_CMD(0x21),
0272     SMART_DAT(0x00),
0273     SMART_DAT(0x00),
0274     SMART_CMD(0x00),    /* Start of Window RAM address set(H) 8*/
0275     SMART_CMD(0x50),
0276     SMART_DAT(0x00),
0277     SMART_DAT(0x00),
0278     SMART_CMD(0x00),    /* End of Window RAM address set(H) 12*/
0279     SMART_CMD(0x51),
0280     SMART_DAT(0x00),
0281     SMART_DAT(0xEF),
0282     SMART_CMD(0x00),    /* Start of Window RAM address set(V) 16*/
0283     SMART_CMD(0x52),
0284     SMART_DAT(0x00),
0285     SMART_DAT(0x00),
0286     SMART_CMD(0x00),    /* End of Window RAM address set(V) 20*/
0287     SMART_CMD(0x53),
0288     SMART_DAT(0x01),
0289     SMART_DAT(0x3F),
0290     SMART_CMD(0x00),    /* Panel interface control 1 */
0291     SMART_CMD(0x90),
0292     SMART_DAT(0x00),
0293     SMART_DAT(0x1A),
0294     SMART_CMD(0x00),    /* Panel interface control 2 */
0295     SMART_CMD(0x92),
0296     SMART_DAT(0x04),
0297     SMART_DAT(0x00),
0298     SMART_CMD(0x00),    /* Panel interface control 3 */
0299     SMART_CMD(0x93),
0300     SMART_DAT(0x00),
0301     SMART_DAT(0x05),
0302     SMART_DELAY(20),
0303 };
0304 
0305 static uint16_t lcd_panel_on[] = {
0306     SMART_CMD(0x00),
0307     SMART_CMD(0x07),
0308     SMART_DAT(0x00),
0309     SMART_DAT(0x21),
0310     SMART_DELAY(1),
0311 
0312     SMART_CMD(0x00),
0313     SMART_CMD(0x07),
0314     SMART_DAT(0x00),
0315     SMART_DAT(0x61),
0316     SMART_DELAY(100),
0317 
0318     SMART_CMD(0x00),
0319     SMART_CMD(0x07),
0320     SMART_DAT(0x01),
0321     SMART_DAT(0x73),
0322     SMART_DELAY(1),
0323 };
0324 
0325 static uint16_t lcd_panel_off[] = {
0326     SMART_CMD(0x00),
0327     SMART_CMD(0x07),
0328     SMART_DAT(0x00),
0329     SMART_DAT(0x72),
0330     SMART_DELAY(40),
0331 
0332     SMART_CMD(0x00),
0333     SMART_CMD(0x07),
0334     SMART_DAT(0x00),
0335     SMART_DAT(0x01),
0336     SMART_DELAY(1),
0337 
0338     SMART_CMD(0x00),
0339     SMART_CMD(0x07),
0340     SMART_DAT(0x00),
0341     SMART_DAT(0x00),
0342     SMART_DELAY(1),
0343 };
0344 
0345 static uint16_t lcd_power_off[] = {
0346     SMART_CMD(0x00),
0347     SMART_CMD(0x10),
0348     SMART_DAT(0x00),
0349     SMART_DAT(0x80),
0350 
0351     SMART_CMD(0x00),
0352     SMART_CMD(0x11),
0353     SMART_DAT(0x01),
0354     SMART_DAT(0x60),
0355 
0356     SMART_CMD(0x00),
0357     SMART_CMD(0x12),
0358     SMART_DAT(0x01),
0359     SMART_DAT(0xAE),
0360     SMART_DELAY(40),
0361 
0362     SMART_CMD(0x00),
0363     SMART_CMD(0x10),
0364     SMART_DAT(0x00),
0365     SMART_DAT(0x00),
0366 };
0367 
0368 static uint16_t update_framedata[] = {
0369     /* set display ram: 240*320 */
0370     SMART_CMD(0x00), /* RAM address set(H) 0*/
0371     SMART_CMD(0x20),
0372     SMART_DAT(0x00),
0373     SMART_DAT(0x00),
0374     SMART_CMD(0x00), /* RAM address set(V) 4*/
0375     SMART_CMD(0x21),
0376     SMART_DAT(0x00),
0377     SMART_DAT(0x00),
0378     SMART_CMD(0x00), /* Start of Window RAM address set(H) 8 */
0379     SMART_CMD(0x50),
0380     SMART_DAT(0x00),
0381     SMART_DAT(0x00),
0382     SMART_CMD(0x00), /* End of Window RAM address set(H) 12 */
0383     SMART_CMD(0x51),
0384     SMART_DAT(0x00),
0385     SMART_DAT(0xEF),
0386     SMART_CMD(0x00), /* Start of Window RAM address set(V) 16 */
0387     SMART_CMD(0x52),
0388     SMART_DAT(0x00),
0389     SMART_DAT(0x00),
0390     SMART_CMD(0x00), /* End of Window RAM address set(V) 20 */
0391     SMART_CMD(0x53),
0392     SMART_DAT(0x01),
0393     SMART_DAT(0x3F),
0394 
0395     /* wait for vsync cmd before transferring frame data */
0396     SMART_CMD_WAIT_FOR_VSYNC,
0397 
0398     /* write ram */
0399     SMART_CMD(0x00),
0400     SMART_CMD(0x22),
0401 
0402     /* write frame data */
0403     SMART_CMD_WRITE_FRAME,
0404 };
0405 
0406 static void ltm022a97a_lcd_power(int on, struct fb_var_screeninfo *var)
0407 {
0408     static int pin_requested = 0;
0409     struct fb_info *info = container_of(var, struct fb_info, var);
0410     int err;
0411 
0412     if (!pin_requested) {
0413         err = gpio_request(GPIO_LCD_RESET, "lcd reset");
0414         if (err) {
0415             pr_err("failed to request gpio for LCD reset\n");
0416             return;
0417         }
0418 
0419         gpio_direction_output(GPIO_LCD_RESET, 0);
0420         pin_requested = 1;
0421     }
0422 
0423     if (on) {
0424         gpio_set_value(GPIO_LCD_RESET, 0); msleep(100);
0425         gpio_set_value(GPIO_LCD_RESET, 1); msleep(10);
0426 
0427         pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_on));
0428         pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_on));
0429     } else {
0430         pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_off));
0431         pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_off));
0432     }
0433 
0434     err = pxafb_smart_flush(info);
0435     if (err)
0436         pr_err("%s: timed out\n", __func__);
0437 }
0438 
0439 static void ltm022a97a_update(struct fb_info *info)
0440 {
0441     pxafb_smart_queue(info, ARRAY_AND_SIZE(update_framedata));
0442     pxafb_smart_flush(info);
0443 }
0444 
0445 static struct pxafb_mode_info toshiba_ltm022a97a_modes[] = {
0446     [0] = {
0447         .xres           = 240,
0448         .yres           = 320,
0449         .bpp            = 16,
0450         .a0csrd_set_hld     = 30,
0451         .a0cswr_set_hld     = 30,
0452         .wr_pulse_width     = 30,
0453         .rd_pulse_width     = 30,
0454         .op_hold_time       = 30,
0455         .cmd_inh_time       = 60,
0456 
0457         /* L_LCLK_A0 and L_LCLK_RD active low */
0458         .sync           = FB_SYNC_HOR_HIGH_ACT |
0459                       FB_SYNC_VERT_HIGH_ACT,
0460     },
0461 };
0462 
0463 static struct pxafb_mach_info saar_lcd_info = {
0464     .modes          = toshiba_ltm022a97a_modes,
0465     .num_modes      = 1,
0466     .lcd_conn       = LCD_SMART_PANEL_8BPP | LCD_PCLK_EDGE_FALL,
0467     .pxafb_lcd_power    = ltm022a97a_lcd_power,
0468     .smart_update       = ltm022a97a_update,
0469 };
0470 
0471 static void __init saar_init_lcd(void)
0472 {
0473     pxa_set_fb_info(NULL, &saar_lcd_info);
0474 }
0475 #else
0476 static inline void saar_init_lcd(void) {}
0477 #endif
0478 
0479 #if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
0480 static struct da9034_backlight_pdata saar_da9034_backlight = {
0481     .output_current = 4,    /* 4mA */
0482 };
0483 
0484 static struct da903x_subdev_info saar_da9034_subdevs[] = {
0485     [0] = {
0486         .name       = "da903x-backlight",
0487         .id     = DA9034_ID_WLED,
0488         .platform_data  = &saar_da9034_backlight,
0489     },
0490 };
0491 
0492 static struct da903x_platform_data saar_da9034_info = {
0493     .num_subdevs    = ARRAY_SIZE(saar_da9034_subdevs),
0494     .subdevs    = saar_da9034_subdevs,
0495 };
0496 
0497 static struct i2c_board_info saar_i2c_info[] = {
0498     [0] = {
0499         .type       = "da9034",
0500         .addr       = 0x34,
0501         .platform_data  = &saar_da9034_info,
0502         .irq        = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)),
0503     },
0504 };
0505 
0506 static void __init saar_init_i2c(void)
0507 {
0508     pxa_set_i2c_info(NULL);
0509     i2c_register_board_info(0, ARRAY_AND_SIZE(saar_i2c_info));
0510 }
0511 #else
0512 static inline void saar_init_i2c(void) {}
0513 #endif
0514 
0515 #if defined(CONFIG_MTD_ONENAND) || defined(CONFIG_MTD_ONENAND_MODULE)
0516 static struct mtd_partition saar_onenand_partitions[] = {
0517     {
0518         .name       = "bootloader",
0519         .offset     = 0,
0520         .size       = SZ_1M,
0521         .mask_flags = MTD_WRITEABLE,
0522     }, {
0523         .name       = "reserved",
0524         .offset     = MTDPART_OFS_APPEND,
0525         .size       = SZ_128K,
0526         .mask_flags = MTD_WRITEABLE,
0527     }, {
0528         .name       = "reserved",
0529         .offset     = MTDPART_OFS_APPEND,
0530         .size       = SZ_8M,
0531         .mask_flags = MTD_WRITEABLE,
0532     }, {
0533         .name       = "kernel",
0534         .offset     = MTDPART_OFS_APPEND,
0535         .size       = (SZ_2M + SZ_1M),
0536         .mask_flags = 0,
0537     }, {
0538         .name       = "filesystem",
0539         .offset     = MTDPART_OFS_APPEND,
0540         .size       = SZ_32M + SZ_16M,
0541         .mask_flags = 0,
0542     }
0543 };
0544 
0545 static struct onenand_platform_data saar_onenand_info = {
0546     .parts      = saar_onenand_partitions,
0547     .nr_parts   = ARRAY_SIZE(saar_onenand_partitions),
0548 };
0549 
0550 #define SMC_CS0_PHYS_BASE   (0x10000000)
0551 
0552 static struct resource saar_resource_onenand[] = {
0553     [0] = {
0554         .start  = SMC_CS0_PHYS_BASE,
0555         .end    = SMC_CS0_PHYS_BASE + SZ_1M,
0556         .flags  = IORESOURCE_MEM,
0557     },
0558 };
0559 
0560 static struct platform_device saar_device_onenand = {
0561     .name       = "onenand-flash",
0562     .id     = -1,
0563     .dev        = {
0564         .platform_data  = &saar_onenand_info,
0565     },
0566     .resource   = saar_resource_onenand,
0567     .num_resources  = ARRAY_SIZE(saar_resource_onenand),
0568 };
0569 
0570 static void __init saar_init_onenand(void)
0571 {
0572     platform_device_register(&saar_device_onenand);
0573 }
0574 #else
0575 static void __init saar_init_onenand(void) {}
0576 #endif
0577 
0578 static void __init saar_init(void)
0579 {
0580     /* initialize MFP configurations */
0581     pxa3xx_mfp_config(ARRAY_AND_SIZE(saar_mfp_cfg));
0582 
0583     pxa_set_ffuart_info(NULL);
0584     pxa_set_btuart_info(NULL);
0585     pxa_set_stuart_info(NULL);
0586 
0587     platform_device_register(&smc91x_device);
0588     saar_init_onenand();
0589 
0590     saar_init_i2c();
0591     saar_init_lcd();
0592 }
0593 
0594 MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
0595     /* Maintainer: Eric Miao <eric.miao@marvell.com> */
0596     .atag_offset    = 0x100,
0597     .map_io         = pxa3xx_map_io,
0598     .nr_irqs    = PXA_NR_IRQS,
0599     .init_irq       = pxa3xx_init_irq,
0600     .handle_irq       = pxa3xx_handle_irq,
0601     .init_time  = pxa_timer_init,
0602     .init_machine   = saar_init,
0603     .restart    = pxa_restart,
0604 MACHINE_END
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