arm/mach-pxa/regs-uart.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ASM_ARCH_REGS_UART_H
0003 #define __ASM_ARCH_REGS_UART_H
0004
0005 #include "pxa-regs.h"
0006
0007 /*
0008  * UARTs
0009  */
0010
0011 /* Full Function UART (FFUART) */
0012 #define FFUART      FFRBR
0013 #define FFRBR       __REG(0x40100000)  /* Receive Buffer Register (read only) */
0014 #define FFTHR       __REG(0x40100000)  /* Transmit Holding Register (write only) */
0015 #define FFIER       __REG(0x40100004)  /* Interrupt Enable Register (read/write) */
0016 #define FFIIR       __REG(0x40100008)  /* Interrupt ID Register (read only) */
0017 #define FFFCR       __REG(0x40100008)  /* FIFO Control Register (write only) */
0018 #define FFLCR       __REG(0x4010000C)  /* Line Control Register (read/write) */
0019 #define FFMCR       __REG(0x40100010)  /* Modem Control Register (read/write) */
0020 #define FFLSR       __REG(0x40100014)  /* Line Status Register (read only) */
0021 #define FFMSR       __REG(0x40100018)  /* Modem Status Register (read only) */
0022 #define FFSPR       __REG(0x4010001C)  /* Scratch Pad Register (read/write) */
0023 #define FFISR       __REG(0x40100020)  /* Infrared Selection Register (read/write) */
0024 #define FFDLL       __REG(0x40100000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
0025 #define FFDLH       __REG(0x40100004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
0026
0027 /* Bluetooth UART (BTUART) */
0028 #define BTUART      BTRBR
0029 #define BTRBR       __REG(0x40200000)  /* Receive Buffer Register (read only) */
0030 #define BTTHR       __REG(0x40200000)  /* Transmit Holding Register (write only) */
0031 #define BTIER       __REG(0x40200004)  /* Interrupt Enable Register (read/write) */
0032 #define BTIIR       __REG(0x40200008)  /* Interrupt ID Register (read only) */
0033 #define BTFCR       __REG(0x40200008)  /* FIFO Control Register (write only) */
0034 #define BTLCR       __REG(0x4020000C)  /* Line Control Register (read/write) */
0035 #define BTMCR       __REG(0x40200010)  /* Modem Control Register (read/write) */
0036 #define BTLSR       __REG(0x40200014)  /* Line Status Register (read only) */
0037 #define BTMSR       __REG(0x40200018)  /* Modem Status Register (read only) */
0038 #define BTSPR       __REG(0x4020001C)  /* Scratch Pad Register (read/write) */
0039 #define BTISR       __REG(0x40200020)  /* Infrared Selection Register (read/write) */
0040 #define BTDLL       __REG(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
0041 #define BTDLH       __REG(0x40200004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
0042
0043 /* Standard UART (STUART) */
0044 #define STUART      STRBR
0045 #define STRBR       __REG(0x40700000)  /* Receive Buffer Register (read only) */
0046 #define STTHR       __REG(0x40700000)  /* Transmit Holding Register (write only) */
0047 #define STIER       __REG(0x40700004)  /* Interrupt Enable Register (read/write) */
0048 #define STIIR       __REG(0x40700008)  /* Interrupt ID Register (read only) */
0049 #define STFCR       __REG(0x40700008)  /* FIFO Control Register (write only) */
0050 #define STLCR       __REG(0x4070000C)  /* Line Control Register (read/write) */
0051 #define STMCR       __REG(0x40700010)  /* Modem Control Register (read/write) */
0052 #define STLSR       __REG(0x40700014)  /* Line Status Register (read only) */
0053 #define STMSR       __REG(0x40700018)  /* Reserved */
0054 #define STSPR       __REG(0x4070001C)  /* Scratch Pad Register (read/write) */
0055 #define STISR       __REG(0x40700020)  /* Infrared Selection Register (read/write) */
0056 #define STDLL       __REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
0057 #define STDLH       __REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
0058
0059 /* Hardware UART (HWUART) */
0060 #define HWUART      HWRBR
0061 #define HWRBR       __REG(0x41600000)  /* Receive Buffer Register (read only) */
0062 #define HWTHR       __REG(0x41600000)  /* Transmit Holding Register (write only) */
0063 #define HWIER       __REG(0x41600004)  /* Interrupt Enable Register (read/write) */
0064 #define HWIIR       __REG(0x41600008)  /* Interrupt ID Register (read only) */
0065 #define HWFCR       __REG(0x41600008)  /* FIFO Control Register (write only) */
0066 #define HWLCR       __REG(0x4160000C)  /* Line Control Register (read/write) */
0067 #define HWMCR       __REG(0x41600010)  /* Modem Control Register (read/write) */
0068 #define HWLSR       __REG(0x41600014)  /* Line Status Register (read only) */
0069 #define HWMSR       __REG(0x41600018)  /* Modem Status Register (read only) */
0070 #define HWSPR       __REG(0x4160001C)  /* Scratch Pad Register (read/write) */
0071 #define HWISR       __REG(0x41600020)  /* Infrared Selection Register (read/write) */
0072 #define HWFOR       __REG(0x41600024)  /* Receive FIFO Occupancy Register (read only) */
0073 #define HWABR       __REG(0x41600028)  /* Auto-Baud Control Register (read/write) */
0074 #define HWACR       __REG(0x4160002C)  /* Auto-Baud Count Register (read only) */
0075 #define HWDLL       __REG(0x41600000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
0076 #define HWDLH       __REG(0x41600004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
0077
0078 #define IER_DMAE    (1 << 7)    /* DMA Requests Enable */
0079 #define IER_UUE     (1 << 6)    /* UART Unit Enable */
0080 #define IER_NRZE    (1 << 5)    /* NRZ coding Enable */
0081 #define IER_RTIOE   (1 << 4)    /* Receiver Time Out Interrupt Enable */
0082 #define IER_MIE     (1 << 3)    /* Modem Interrupt Enable */
0083 #define IER_RLSE    (1 << 2)    /* Receiver Line Status Interrupt Enable */
0084 #define IER_TIE     (1 << 1)    /* Transmit Data request Interrupt Enable */
0085 #define IER_RAVIE   (1 << 0)    /* Receiver Data Available Interrupt Enable */
0086
0087 #define IIR_FIFOES1 (1 << 7)    /* FIFO Mode Enable Status */
0088 #define IIR_FIFOES0 (1 << 6)    /* FIFO Mode Enable Status */
0089 #define IIR_TOD     (1 << 3)    /* Time Out Detected */
0090 #define IIR_IID2    (1 << 2)    /* Interrupt Source Encoded */
0091 #define IIR_IID1    (1 << 1)    /* Interrupt Source Encoded */
0092 #define IIR_IP      (1 << 0)    /* Interrupt Pending (active low) */
0093
0094 #define FCR_ITL2    (1 << 7)    /* Interrupt Trigger Level */
0095 #define FCR_ITL1    (1 << 6)    /* Interrupt Trigger Level */
0096 #define FCR_RESETTF (1 << 2)    /* Reset Transmitter FIFO */
0097 #define FCR_RESETRF (1 << 1)    /* Reset Receiver FIFO */
0098 #define FCR_TRFIFOE (1 << 0)    /* Transmit and Receive FIFO Enable */
0099 #define FCR_ITL_1   (0)
0100 #define FCR_ITL_8   (FCR_ITL1)
0101 #define FCR_ITL_16  (FCR_ITL2)
0102 #define FCR_ITL_32  (FCR_ITL2|FCR_ITL1)
0103
0104 #define LCR_DLAB    (1 << 7)    /* Divisor Latch Access Bit */
0105 #define LCR_SB      (1 << 6)    /* Set Break */
0106 #define LCR_STKYP   (1 << 5)    /* Sticky Parity */
0107 #define LCR_EPS     (1 << 4)    /* Even Parity Select */
0108 #define LCR_PEN     (1 << 3)    /* Parity Enable */
0109 #define LCR_STB     (1 << 2)    /* Stop Bit */
0110 #define LCR_WLS1    (1 << 1)    /* Word Length Select */
0111 #define LCR_WLS0    (1 << 0)    /* Word Length Select */
0112
0113 #define LSR_FIFOE   (1 << 7)    /* FIFO Error Status */
0114 #define LSR_TEMT    (1 << 6)    /* Transmitter Empty */
0115 #define LSR_TDRQ    (1 << 5)    /* Transmit Data Request */
0116 #define LSR_BI      (1 << 4)    /* Break Interrupt */
0117 #define LSR_FE      (1 << 3)    /* Framing Error */
0118 #define LSR_PE      (1 << 2)    /* Parity Error */
0119 #define LSR_OE      (1 << 1)    /* Overrun Error */
0120 #define LSR_DR      (1 << 0)    /* Data Ready */
0121
0122 #define MCR_LOOP    (1 << 4)
0123 #define MCR_OUT2    (1 << 3)    /* force MSR_DCD in loopback mode */
0124 #define MCR_OUT1    (1 << 2)    /* force MSR_RI in loopback mode */
0125 #define MCR_RTS     (1 << 1)    /* Request to Send */
0126 #define MCR_DTR     (1 << 0)    /* Data Terminal Ready */
0127
0128 #define MSR_DCD     (1 << 7)    /* Data Carrier Detect */
0129 #define MSR_RI      (1 << 6)    /* Ring Indicator */
0130 #define MSR_DSR     (1 << 5)    /* Data Set Ready */
0131 #define MSR_CTS     (1 << 4)    /* Clear To Send */
0132 #define MSR_DDCD    (1 << 3)    /* Delta Data Carrier Detect */
0133 #define MSR_TERI    (1 << 2)    /* Trailing Edge Ring Indicator */
0134 #define MSR_DDSR    (1 << 1)    /* Delta Data Set Ready */
0135 #define MSR_DCTS    (1 << 0)    /* Delta Clear To Send */
0136
0137 /*
0138  * IrSR (Infrared Selection Register)
0139  */
0140 #define STISR_RXPL      (1 << 4)        /* Receive Data Polarity */
0141 #define STISR_TXPL      (1 << 3)        /* Transmit Data Polarity */
0142 #define STISR_XMODE     (1 << 2)        /* Transmit Pulse Width Select */
0143 #define STISR_RCVEIR    (1 << 1)        /* Receiver SIR Enable */
0144 #define STISR_XMITIR    (1 << 0)        /* Transmitter SIR Enable */
0145
0146 #endif /* __ASM_ARCH_REGS_UART_H */