arm/mach-pxa/regs-ost.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ASM_MACH_REGS_OST_H
0003 #define __ASM_MACH_REGS_OST_H
0004
0005 #include "pxa-regs.h"
0006
0007 /*
0008  * OS Timer & Match Registers
0009  */
0010 #define OST_PHYS    0x40A00000
0011 #define OST_LEN     0x00000020
0012
0013 #define OSMR0       io_p2v(0x40A00000)  /* */
0014 #define OSMR1       io_p2v(0x40A00004)  /* */
0015 #define OSMR2       io_p2v(0x40A00008)  /* */
0016 #define OSMR3       io_p2v(0x40A0000C)  /* */
0017 #define OSMR4       io_p2v(0x40A00080)  /* */
0018 #define OSCR        io_p2v(0x40A00010)  /* OS Timer Counter Register */
0019 #define OSCR4       io_p2v(0x40A00040)  /* OS Timer Counter Register */
0020 #define OMCR4       io_p2v(0x40A000C0)  /* */
0021 #define OSSR        io_p2v(0x40A00014)  /* OS Timer Status Register */
0022 #define OWER        io_p2v(0x40A00018)  /* OS Timer Watchdog Enable Register */
0023 #define OIER        io_p2v(0x40A0001C)  /* OS Timer Interrupt Enable Register */
0024
0025 #define OSSR_M3     (1 << 3)    /* Match status channel 3 */
0026 #define OSSR_M2     (1 << 2)    /* Match status channel 2 */
0027 #define OSSR_M1     (1 << 1)    /* Match status channel 1 */
0028 #define OSSR_M0     (1 << 0)    /* Match status channel 0 */
0029
0030 #define OWER_WME    (1 << 0)    /* Watchdog Match Enable */
0031
0032 #define OIER_E3     (1 << 3)    /* Interrupt enable channel 3 */
0033 #define OIER_E2     (1 << 2)    /* Interrupt enable channel 2 */
0034 #define OIER_E1     (1 << 1)    /* Interrupt enable channel 1 */
0035 #define OIER_E0     (1 << 0)    /* Interrupt enable channel 0 */
0036
0037 #endif /* __ASM_MACH_REGS_OST_H */