arm/mach-pxa/pxa3xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * linux/arch/arm/mach-pxa/pxa3xx.c
0004  *
0005  * code specific to pxa3xx aka Monahans
0006  *
0007  * Copyright (C) 2006 Marvell International Ltd.
0008  *
0009  * 2007-09-02: eric miao <eric.miao@marvell.com>
0010  *             initial version
0011  */
0012 #include <linux/dmaengine.h>
0013 #include <linux/dma/pxa-dma.h>
0014 #include <linux/module.h>
0015 #include <linux/kernel.h>
0016 #include <linux/init.h>
0017 #include <linux/gpio-pxa.h>
0018 #include <linux/pm.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/irq.h>
0021 #include <linux/irqchip.h>
0022 #include <linux/io.h>
0023 #include <linux/of.h>
0024 #include <linux/syscore_ops.h>
0025 #include <linux/platform_data/i2c-pxa.h>
0026 #include <linux/platform_data/mmp_dma.h>
0027 #include <linux/soc/pxa/cpu.h>
0028 #include <linux/clk/pxa.h>
0029
0030 #include <asm/mach/map.h>
0031 #include <asm/suspend.h>
0032 #include "pxa3xx-regs.h"
0033 #include "reset.h"
0034 #include <linux/platform_data/usb-ohci-pxa27x.h>
0035 #include "pm.h"
0036 #include "addr-map.h"
0037 #include "smemc.h"
0038 #include "irqs.h"
0039
0040 #include "generic.h"
0041 #include "devices.h"
0042
0043 #define PECR_IE(n)  ((1 << ((n) * 2)) << 28)
0044 #define PECR_IS(n)  ((1 << ((n) * 2)) << 29)
0045
0046 extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
0047
0048 /*
0049  * NAND NFC: DFI bus arbitration subset
0050  */
0051 #define NDCR            (*(volatile u32 __iomem*)(NAND_VIRT + 0))
0052 #define NDCR_ND_ARB_EN      (1 << 12)
0053 #define NDCR_ND_ARB_CNTL    (1 << 19)
0054
0055 #define CKEN_BOOT       11      /* < Boot rom clock enable */
0056 #define CKEN_TPM        19      /* < TPM clock enable */
0057 #define CKEN_HSIO2      41      /* < HSIO2 clock enable */
0058
0059 #ifdef CONFIG_PM
0060
0061 #define ISRAM_START 0x5c000000
0062 #define ISRAM_SIZE  SZ_256K
0063
0064 static void __iomem *sram;
0065 static unsigned long wakeup_src;
0066
0067 /*
0068  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
0069  * memory controller has to be reinitialised, so we place some code
0070  * in the SRAM to perform this function.
0071  *
0072  * We disable FIQs across the standby - otherwise, we might receive a
0073  * FIQ while the SDRAM is unavailable.
0074  */
0075 static void pxa3xx_cpu_standby(unsigned int pwrmode)
0076 {
0077     void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
0078
0079     memcpy_toio(sram + 0x8000, pm_enter_standby_start,
0080             pm_enter_standby_end - pm_enter_standby_start);
0081
0082     AD2D0SR = ~0;
0083     AD2D1SR = ~0;
0084     AD2D0ER = wakeup_src;
0085     AD2D1ER = 0;
0086     ASCR = ASCR;
0087     ARSR = ARSR;
0088
0089     local_fiq_disable();
0090     fn(pwrmode);
0091     local_fiq_enable();
0092
0093     AD2D0ER = 0;
0094     AD2D1ER = 0;
0095 }
0096
0097 /*
0098  * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
0099  * PXA3xx development kits assumes that the resuming process continues
0100  * with the address stored within the first 4 bytes of SDRAM. The PSPR
0101  * register is used privately by BootROM and OBM, and _must_ be set to
0102  * 0x5c014000 for the moment.
0103  */
0104 static void pxa3xx_cpu_pm_suspend(void)
0105 {
0106     volatile unsigned long *p = (volatile void *)0xc0000000;
0107     unsigned long saved_data = *p;
0108 #ifndef CONFIG_IWMMXT
0109     u64 acc0;
0110
0111     asm volatile(".arch_extension xscale\n\t"
0112              "mra %Q0, %R0, acc0" : "=r" (acc0));
0113 #endif
0114
0115     /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
0116     CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
0117     CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
0118
0119     /* clear and setup wakeup source */
0120     AD3SR = ~0;
0121     AD3ER = wakeup_src;
0122     ASCR = ASCR;
0123     ARSR = ARSR;
0124
0125     PCFR |= (1u << 13);         /* L1_DIS */
0126     PCFR &= ~((1u << 12) | (1u << 1));  /* L0_EN | SL_ROD */
0127
0128     PSPR = 0x5c014000;
0129
0130     /* overwrite with the resume address */
0131     *p = __pa_symbol(cpu_resume);
0132
0133     cpu_suspend(0, pxa3xx_finish_suspend);
0134
0135     *p = saved_data;
0136
0137     AD3ER = 0;
0138
0139 #ifndef CONFIG_IWMMXT
0140     asm volatile(".arch_extension xscale\n\t"
0141              "mar acc0, %Q0, %R0" : "=r" (acc0));
0142 #endif
0143 }
0144
0145 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
0146 {
0147     /*
0148      * Don't sleep if no wakeup sources are defined
0149      */
0150     if (wakeup_src == 0) {
0151         printk(KERN_ERR "Not suspending: no wakeup sources\n");
0152         return;
0153     }
0154
0155     switch (state) {
0156     case PM_SUSPEND_STANDBY:
0157         pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
0158         break;
0159
0160     case PM_SUSPEND_MEM:
0161         pxa3xx_cpu_pm_suspend();
0162         break;
0163     }
0164 }
0165
0166 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
0167 {
0168     return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
0169 }
0170
0171 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
0172     .valid      = pxa3xx_cpu_pm_valid,
0173     .enter      = pxa3xx_cpu_pm_enter,
0174 };
0175
0176 static void __init pxa3xx_init_pm(void)
0177 {
0178     sram = ioremap(ISRAM_START, ISRAM_SIZE);
0179     if (!sram) {
0180         printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
0181         return;
0182     }
0183
0184     /*
0185      * Since we copy wakeup code into the SRAM, we need to ensure
0186      * that it is preserved over the low power modes.  Note: bit 8
0187      * is undocumented in the developer manual, but must be set.
0188      */
0189     AD1R |= ADXR_L2 | ADXR_R0;
0190     AD2R |= ADXR_L2 | ADXR_R0;
0191     AD3R |= ADXR_L2 | ADXR_R0;
0192
0193     /*
0194      * Clear the resume enable registers.
0195      */
0196     AD1D0ER = 0;
0197     AD2D0ER = 0;
0198     AD2D1ER = 0;
0199     AD3ER = 0;
0200
0201     pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
0202 }
0203
0204 static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
0205 {
0206     unsigned long flags, mask = 0;
0207
0208     switch (d->irq) {
0209     case IRQ_SSP3:
0210         mask = ADXER_MFP_WSSP3;
0211         break;
0212     case IRQ_MSL:
0213         mask = ADXER_WMSL0;
0214         break;
0215     case IRQ_USBH2:
0216     case IRQ_USBH1:
0217         mask = ADXER_WUSBH;
0218         break;
0219     case IRQ_KEYPAD:
0220         mask = ADXER_WKP;
0221         break;
0222     case IRQ_AC97:
0223         mask = ADXER_MFP_WAC97;
0224         break;
0225     case IRQ_USIM:
0226         mask = ADXER_WUSIM0;
0227         break;
0228     case IRQ_SSP2:
0229         mask = ADXER_MFP_WSSP2;
0230         break;
0231     case IRQ_I2C:
0232         mask = ADXER_MFP_WI2C;
0233         break;
0234     case IRQ_STUART:
0235         mask = ADXER_MFP_WUART3;
0236         break;
0237     case IRQ_BTUART:
0238         mask = ADXER_MFP_WUART2;
0239         break;
0240     case IRQ_FFUART:
0241         mask = ADXER_MFP_WUART1;
0242         break;
0243     case IRQ_MMC:
0244         mask = ADXER_MFP_WMMC1;
0245         break;
0246     case IRQ_SSP:
0247         mask = ADXER_MFP_WSSP1;
0248         break;
0249     case IRQ_RTCAlrm:
0250         mask = ADXER_WRTC;
0251         break;
0252     case IRQ_SSP4:
0253         mask = ADXER_MFP_WSSP4;
0254         break;
0255     case IRQ_TSI:
0256         mask = ADXER_WTSI;
0257         break;
0258     case IRQ_USIM2:
0259         mask = ADXER_WUSIM1;
0260         break;
0261     case IRQ_MMC2:
0262         mask = ADXER_MFP_WMMC2;
0263         break;
0264     case IRQ_NAND:
0265         mask = ADXER_MFP_WFLASH;
0266         break;
0267     case IRQ_USB2:
0268         mask = ADXER_WUSB2;
0269         break;
0270     case IRQ_WAKEUP0:
0271         mask = ADXER_WEXTWAKE0;
0272         break;
0273     case IRQ_WAKEUP1:
0274         mask = ADXER_WEXTWAKE1;
0275         break;
0276     case IRQ_MMC3:
0277         mask = ADXER_MFP_GEN12;
0278         break;
0279     default:
0280         return -EINVAL;
0281     }
0282
0283     local_irq_save(flags);
0284     if (on)
0285         wakeup_src |= mask;
0286     else
0287         wakeup_src &= ~mask;
0288     local_irq_restore(flags);
0289
0290     return 0;
0291 }
0292 #else
0293 static inline void pxa3xx_init_pm(void) {}
0294 #define pxa3xx_set_wake NULL
0295 #endif
0296
0297 static void pxa_ack_ext_wakeup(struct irq_data *d)
0298 {
0299     PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
0300 }
0301
0302 static void pxa_mask_ext_wakeup(struct irq_data *d)
0303 {
0304     pxa_mask_irq(d);
0305     PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
0306 }
0307
0308 static void pxa_unmask_ext_wakeup(struct irq_data *d)
0309 {
0310     pxa_unmask_irq(d);
0311     PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
0312 }
0313
0314 static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
0315 {
0316     if (flow_type & IRQ_TYPE_EDGE_RISING)
0317         PWER |= 1 << (d->irq - IRQ_WAKEUP0);
0318
0319     if (flow_type & IRQ_TYPE_EDGE_FALLING)
0320         PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
0321
0322     return 0;
0323 }
0324
0325 static struct irq_chip pxa_ext_wakeup_chip = {
0326     .name       = "WAKEUP",
0327     .irq_ack    = pxa_ack_ext_wakeup,
0328     .irq_mask   = pxa_mask_ext_wakeup,
0329     .irq_unmask = pxa_unmask_ext_wakeup,
0330     .irq_set_type   = pxa_set_ext_wakeup_type,
0331 };
0332
0333 static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
0334                        unsigned int))
0335 {
0336     int irq;
0337
0338     for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
0339         irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
0340                      handle_edge_irq);
0341         irq_clear_status_flags(irq, IRQ_NOREQUEST);
0342     }
0343
0344     pxa_ext_wakeup_chip.irq_set_wake = fn;
0345 }
0346
0347 static void __init __pxa3xx_init_irq(void)
0348 {
0349     /* enable CP6 access */
0350     u32 value;
0351     __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
0352     value |= (1 << 6);
0353     __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
0354
0355     pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
0356 }
0357
0358 void __init pxa3xx_init_irq(void)
0359 {
0360     __pxa3xx_init_irq();
0361     pxa_init_irq(56, pxa3xx_set_wake);
0362 }
0363
0364 #ifdef CONFIG_OF
0365 static int __init __init
0366 pxa3xx_dt_init_irq(struct device_node *node, struct device_node *parent)
0367 {
0368     __pxa3xx_init_irq();
0369     pxa_dt_irq_init(pxa3xx_set_wake);
0370     set_handle_irq(ichp_handle_irq);
0371
0372     return 0;
0373 }
0374 IRQCHIP_DECLARE(pxa3xx_intc, "marvell,pxa-intc", pxa3xx_dt_init_irq);
0375 #endif  /* CONFIG_OF */
0376
0377 static struct map_desc pxa3xx_io_desc[] __initdata = {
0378     {   /* Mem Ctl */
0379         .virtual    = (unsigned long)SMEMC_VIRT,
0380         .pfn        = __phys_to_pfn(PXA3XX_SMEMC_BASE),
0381         .length     = SMEMC_SIZE,
0382         .type       = MT_DEVICE
0383     }, {
0384         .virtual    = (unsigned long)NAND_VIRT,
0385         .pfn        = __phys_to_pfn(NAND_PHYS),
0386         .length     = NAND_SIZE,
0387         .type       = MT_DEVICE
0388     },
0389 };
0390
0391 void __init pxa3xx_map_io(void)
0392 {
0393     pxa_map_io();
0394     iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
0395     pxa3xx_get_clk_frequency_khz(1);
0396 }
0397
0398 /*
0399  * device registration specific to PXA3xx.
0400  */
0401
0402 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
0403 {
0404     pxa_register_device(&pxa3xx_device_i2c_power, info);
0405 }
0406
0407 static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = {
0408     .irq_base   = PXA_GPIO_TO_IRQ(0),
0409 };
0410
0411 static struct platform_device *devices[] __initdata = {
0412     &pxa27x_device_udc,
0413     &pxa_device_pmu,
0414     &pxa_device_i2s,
0415     &pxa_device_asoc_ssp1,
0416     &pxa_device_asoc_ssp2,
0417     &pxa_device_asoc_ssp3,
0418     &pxa_device_asoc_ssp4,
0419     &pxa_device_asoc_platform,
0420     &pxa_device_rtc,
0421     &pxa3xx_device_ssp1,
0422     &pxa3xx_device_ssp2,
0423     &pxa3xx_device_ssp3,
0424     &pxa3xx_device_ssp4,
0425     &pxa27x_device_pwm0,
0426     &pxa27x_device_pwm1,
0427 };
0428
0429 static const struct dma_slave_map pxa3xx_slave_map[] = {
0430     /* PXA25x, PXA27x and PXA3xx common entries */
0431     { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
0432     { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
0433     { "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
0434       PDMA_FILTER_PARAM(LOWEST, 10) },
0435     { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
0436     { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
0437     { "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
0438     { "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
0439     { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
0440     { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
0441     { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
0442     { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
0443     { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
0444     { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
0445     { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) },
0446     { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) },
0447
0448     /* PXA3xx specific map */
0449     { "pxa-ssp-dai.3", "rx", PDMA_FILTER_PARAM(LOWEST, 2) },
0450     { "pxa-ssp-dai.3", "tx", PDMA_FILTER_PARAM(LOWEST, 3) },
0451     { "pxa2xx-mci.1", "rx", PDMA_FILTER_PARAM(LOWEST, 93) },
0452     { "pxa2xx-mci.1", "tx", PDMA_FILTER_PARAM(LOWEST, 94) },
0453     { "pxa3xx-nand", "data", PDMA_FILTER_PARAM(LOWEST, 97) },
0454     { "pxa2xx-mci.2", "rx", PDMA_FILTER_PARAM(LOWEST, 100) },
0455     { "pxa2xx-mci.2", "tx", PDMA_FILTER_PARAM(LOWEST, 101) },
0456 };
0457
0458 static struct mmp_dma_platdata pxa3xx_dma_pdata = {
0459     .dma_channels   = 32,
0460     .nb_requestors  = 100,
0461     .slave_map  = pxa3xx_slave_map,
0462     .slave_map_cnt  = ARRAY_SIZE(pxa3xx_slave_map),
0463 };
0464
0465 static int __init pxa3xx_init(void)
0466 {
0467     int ret = 0;
0468
0469     if (cpu_is_pxa3xx()) {
0470
0471         pxa_register_wdt(ARSR);
0472
0473         /*
0474          * clear RDH bit every time after reset
0475          *
0476          * Note: the last 3 bits DxS are write-1-to-clear so carefully
0477          * preserve them here in case they will be referenced later
0478          */
0479         ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
0480
0481         /*
0482          * Disable DFI bus arbitration, to prevent a system bus lock if
0483          * somebody disables the NAND clock (unused clock) while this
0484          * bit remains set.
0485          */
0486         NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL;
0487
0488         pxa3xx_init_pm();
0489
0490         enable_irq_wake(IRQ_WAKEUP0);
0491         if (cpu_is_pxa320())
0492             enable_irq_wake(IRQ_WAKEUP1);
0493
0494         register_syscore_ops(&pxa_irq_syscore_ops);
0495         register_syscore_ops(&pxa3xx_mfp_syscore_ops);
0496
0497         if (of_have_populated_dt())
0498             return 0;
0499
0500         pxa2xx_set_dmac_info(&pxa3xx_dma_pdata);
0501         ret = platform_add_devices(devices, ARRAY_SIZE(devices));
0502         if (ret)
0503             return ret;
0504         if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) {
0505             platform_device_add_data(&pxa3xx_device_gpio,
0506                          &pxa3xx_gpio_pdata,
0507                          sizeof(pxa3xx_gpio_pdata));
0508             ret = platform_device_register(&pxa3xx_device_gpio);
0509         }
0510     }
0511
0512     return ret;
0513 }
0514
0515 postcore_initcall(pxa3xx_init);