arm/mach-pxa/pxa3xx-regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
0004  *
0005  * PXA3xx specific register definitions
0006  *
0007  * Copyright (C) 2007 Marvell International Ltd.
0008  */
0009
0010 #ifndef __ASM_ARCH_PXA3XX_REGS_H
0011 #define __ASM_ARCH_PXA3XX_REGS_H
0012
0013 #include "pxa-regs.h"
0014
0015 /*
0016  * Oscillator Configuration Register (OSCC)
0017  */
0018 #define OSCC           io_p2v(0x41350000)  /* Oscillator Configuration Register */
0019
0020 #define OSCC_PEN       (1 << 11)       /* 13MHz POUT */
0021
0022
0023 /*
0024  * Service Power Management Unit (MPMU)
0025  */
0026 #define PMCR        __REG(0x40F50000)   /* Power Manager Control Register */
0027 #define PSR     __REG(0x40F50004)   /* Power Manager S2 Status Register */
0028 #define PSPR        __REG(0x40F50008)   /* Power Manager Scratch Pad Register */
0029 #define PCFR        __REG(0x40F5000C)   /* Power Manager General Configuration Register */
0030 #define PWER        __REG(0x40F50010)   /* Power Manager Wake-up Enable Register */
0031 #define PWSR        __REG(0x40F50014)   /* Power Manager Wake-up Status Register */
0032 #define PECR        __REG(0x40F50018)   /* Power Manager EXT_WAKEUP[1:0] Control Register */
0033 #define DCDCSR      __REG(0x40F50080)   /* DC-DC Controller Status Register */
0034 #define PVCR        __REG(0x40F50100)   /* Power Manager Voltage Change Control Register */
0035 #define PCMD(x)     __REG(0x40F50110 + ((x) << 2))
0036
0037 /*
0038  * Slave Power Management Unit
0039  */
0040 #define ASCR        __REG(0x40f40000)   /* Application Subsystem Power Status/Configuration */
0041 #define ARSR        __REG(0x40f40004)   /* Application Subsystem Reset Status */
0042 #define AD3ER       __REG(0x40f40008)   /* Application Subsystem Wake-Up from D3 Enable */
0043 #define AD3SR       __REG(0x40f4000c)   /* Application Subsystem Wake-Up from D3 Status */
0044 #define AD2D0ER     __REG(0x40f40010)   /* Application Subsystem Wake-Up from D2 to D0 Enable */
0045 #define AD2D0SR     __REG(0x40f40014)   /* Application Subsystem Wake-Up from D2 to D0 Status */
0046 #define AD2D1ER     __REG(0x40f40018)   /* Application Subsystem Wake-Up from D2 to D1 Enable */
0047 #define AD2D1SR     __REG(0x40f4001c)   /* Application Subsystem Wake-Up from D2 to D1 Status */
0048 #define AD1D0ER     __REG(0x40f40020)   /* Application Subsystem Wake-Up from D1 to D0 Enable */
0049 #define AD1D0SR     __REG(0x40f40024)   /* Application Subsystem Wake-Up from D1 to D0 Status */
0050 #define AGENP       __REG(0x40f4002c)   /* Application Subsystem General Purpose */
0051 #define AD3R        __REG(0x40f40030)   /* Application Subsystem D3 Configuration */
0052 #define AD2R        __REG(0x40f40034)   /* Application Subsystem D2 Configuration */
0053 #define AD1R        __REG(0x40f40038)   /* Application Subsystem D1 Configuration */
0054
0055 /*
0056  * Application Subsystem Configuration bits.
0057  */
0058 #define ASCR_RDH        (1 << 31)
0059 #define ASCR_D1S        (1 << 2)
0060 #define ASCR_D2S        (1 << 1)
0061 #define ASCR_D3S        (1 << 0)
0062
0063 /*
0064  * Application Reset Status bits.
0065  */
0066 #define ARSR_GPR        (1 << 3)
0067 #define ARSR_LPMR       (1 << 2)
0068 #define ARSR_WDT        (1 << 1)
0069 #define ARSR_HWR        (1 << 0)
0070
0071 /*
0072  * Application Subsystem Wake-Up bits.
0073  */
0074 #define ADXER_WRTC      (1 << 31)   /* RTC */
0075 #define ADXER_WOST      (1 << 30)   /* OS Timer */
0076 #define ADXER_WTSI      (1 << 29)   /* Touchscreen */
0077 #define ADXER_WUSBH     (1 << 28)   /* USB host */
0078 #define ADXER_WUSB2     (1 << 26)   /* USB client 2.0 */
0079 #define ADXER_WMSL0     (1 << 24)   /* MSL port 0*/
0080 #define ADXER_WDMUX3        (1 << 23)   /* USB EDMUX3 */
0081 #define ADXER_WDMUX2        (1 << 22)   /* USB EDMUX2 */
0082 #define ADXER_WKP       (1 << 21)   /* Keypad */
0083 #define ADXER_WUSIM1        (1 << 20)   /* USIM Port 1 */
0084 #define ADXER_WUSIM0        (1 << 19)   /* USIM Port 0 */
0085 #define ADXER_WOTG      (1 << 16)   /* USBOTG input */
0086 #define ADXER_MFP_WFLASH    (1 << 15)   /* MFP: Data flash busy */
0087 #define ADXER_MFP_GEN12     (1 << 14)   /* MFP: MMC3/GPIO/OST inputs */
0088 #define ADXER_MFP_WMMC2     (1 << 13)   /* MFP: MMC2 */
0089 #define ADXER_MFP_WMMC1     (1 << 12)   /* MFP: MMC1 */
0090 #define ADXER_MFP_WI2C      (1 << 11)   /* MFP: I2C */
0091 #define ADXER_MFP_WSSP4     (1 << 10)   /* MFP: SSP4 */
0092 #define ADXER_MFP_WSSP3     (1 << 9)    /* MFP: SSP3 */
0093 #define ADXER_MFP_WMAXTRIX  (1 << 8)    /* MFP: matrix keypad */
0094 #define ADXER_MFP_WUART3    (1 << 7)    /* MFP: UART3 */
0095 #define ADXER_MFP_WUART2    (1 << 6)    /* MFP: UART2 */
0096 #define ADXER_MFP_WUART1    (1 << 5)    /* MFP: UART1 */
0097 #define ADXER_MFP_WSSP2     (1 << 4)    /* MFP: SSP2 */
0098 #define ADXER_MFP_WSSP1     (1 << 3)    /* MFP: SSP1 */
0099 #define ADXER_MFP_WAC97     (1 << 2)    /* MFP: AC97 */
0100 #define ADXER_WEXTWAKE1     (1 << 1)    /* External Wake 1 */
0101 #define ADXER_WEXTWAKE0     (1 << 0)    /* External Wake 0 */
0102
0103 /*
0104  * AD3R/AD2R/AD1R bits.  R2-R5 are only defined for PXA320.
0105  */
0106 #define ADXR_L2         (1 << 8)
0107 #define ADXR_R5         (1 << 5)
0108 #define ADXR_R4         (1 << 4)
0109 #define ADXR_R3         (1 << 3)
0110 #define ADXR_R2         (1 << 2)
0111 #define ADXR_R1         (1 << 1)
0112 #define ADXR_R0         (1 << 0)
0113
0114 /*
0115  * Values for PWRMODE CP15 register
0116  */
0117 #define PXA3xx_PM_S3D4C4    0x07    /* aka deep sleep */
0118 #define PXA3xx_PM_S2D3C4    0x06    /* aka sleep */
0119 #define PXA3xx_PM_S0D2C2    0x03    /* aka standby */
0120 #define PXA3xx_PM_S0D1C2    0x02    /* aka LCD refresh */
0121 #define PXA3xx_PM_S0D0C1    0x01
0122
0123 /*
0124  * Application Subsystem Clock
0125  */
0126 #define ACCR        __REG(0x41340000)   /* Application Subsystem Clock Configuration Register */
0127 #define ACSR        __REG(0x41340004)   /* Application Subsystem Clock Status Register */
0128 #define AICSR       __REG(0x41340008)   /* Application Subsystem Interrupt Control/Status Register */
0129 #define CKENA       __REG(0x4134000C)   /* A Clock Enable Register */
0130 #define CKENB       __REG(0x41340010)   /* B Clock Enable Register */
0131 #define CKENC       __REG(0x41340024)   /* C Clock Enable Register */
0132 #define AC97_DIV    __REG(0x41340014)   /* AC97 clock divisor value register */
0133
0134 #endif /* __ASM_ARCH_PXA3XX_REGS_H */