arm/mach-pxa/pxa2xx-regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
0004  *
0005  *  Taken from pxa-regs.h by Russell King
0006  *
0007  *  Author: Nicolas Pitre
0008  *  Copyright:  MontaVista Software Inc.
0009  */
0010
0011 #ifndef __PXA2XX_REGS_H
0012 #define __PXA2XX_REGS_H
0013
0014 #include "pxa-regs.h"
0015
0016 /*
0017  * Power Manager
0018  */
0019
0020 #define PMCR        __REG(0x40F00000)  /* Power Manager Control Register */
0021 #define PSSR        __REG(0x40F00004)  /* Power Manager Sleep Status Register */
0022 #define PSPR        __REG(0x40F00008)  /* Power Manager Scratch Pad Register */
0023 #define PWER        __REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
0024 #define PRER        __REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
0025 #define PFER        __REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
0026 #define PEDR        __REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
0027 #define PCFR        __REG(0x40F0001C)  /* Power Manager General Configuration Register */
0028 #define PGSR0       __REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
0029 #define PGSR1       __REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
0030 #define PGSR2       __REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
0031 #define PGSR3       __REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
0032 #define RCSR        __REG(0x40F00030)  /* Reset Controller Status Register */
0033
0034 #define PSLR        __REG(0x40F00034)   /* Power Manager Sleep Config Register */
0035 #define PSTR        __REG(0x40F00038)   /* Power Manager Standby Config Register */
0036 #define PSNR        __REG(0x40F0003C)   /* Power Manager Sense Config Register */
0037 #define PVCR        __REG(0x40F00040)   /* Power Manager VoltageControl Register */
0038 #define PKWR        __REG(0x40F00050)   /* Power Manager KB Wake-up Enable Reg */
0039 #define PKSR        __REG(0x40F00054)   /* Power Manager KB Level-Detect Register */
0040 #define PCMD(x) __REG2(0x40F00080, (x)<<2)
0041 #define PCMD0   __REG(0x40F00080 + 0 * 4)
0042 #define PCMD1   __REG(0x40F00080 + 1 * 4)
0043 #define PCMD2   __REG(0x40F00080 + 2 * 4)
0044 #define PCMD3   __REG(0x40F00080 + 3 * 4)
0045 #define PCMD4   __REG(0x40F00080 + 4 * 4)
0046 #define PCMD5   __REG(0x40F00080 + 5 * 4)
0047 #define PCMD6   __REG(0x40F00080 + 6 * 4)
0048 #define PCMD7   __REG(0x40F00080 + 7 * 4)
0049 #define PCMD8   __REG(0x40F00080 + 8 * 4)
0050 #define PCMD9   __REG(0x40F00080 + 9 * 4)
0051 #define PCMD10  __REG(0x40F00080 + 10 * 4)
0052 #define PCMD11  __REG(0x40F00080 + 11 * 4)
0053 #define PCMD12  __REG(0x40F00080 + 12 * 4)
0054 #define PCMD13  __REG(0x40F00080 + 13 * 4)
0055 #define PCMD14  __REG(0x40F00080 + 14 * 4)
0056 #define PCMD15  __REG(0x40F00080 + 15 * 4)
0057 #define PCMD16  __REG(0x40F00080 + 16 * 4)
0058 #define PCMD17  __REG(0x40F00080 + 17 * 4)
0059 #define PCMD18  __REG(0x40F00080 + 18 * 4)
0060 #define PCMD19  __REG(0x40F00080 + 19 * 4)
0061 #define PCMD20  __REG(0x40F00080 + 20 * 4)
0062 #define PCMD21  __REG(0x40F00080 + 21 * 4)
0063 #define PCMD22  __REG(0x40F00080 + 22 * 4)
0064 #define PCMD23  __REG(0x40F00080 + 23 * 4)
0065 #define PCMD24  __REG(0x40F00080 + 24 * 4)
0066 #define PCMD25  __REG(0x40F00080 + 25 * 4)
0067 #define PCMD26  __REG(0x40F00080 + 26 * 4)
0068 #define PCMD27  __REG(0x40F00080 + 27 * 4)
0069 #define PCMD28  __REG(0x40F00080 + 28 * 4)
0070 #define PCMD29  __REG(0x40F00080 + 29 * 4)
0071 #define PCMD30  __REG(0x40F00080 + 30 * 4)
0072 #define PCMD31  __REG(0x40F00080 + 31 * 4)
0073
0074 #define PCMD_MBC    (1<<12)
0075 #define PCMD_DCE    (1<<11)
0076 #define PCMD_LC (1<<10)
0077 /* FIXME:  PCMD_SQC need be checked.   */
0078 #define PCMD_SQC    (3<<8)  /* currently only bit 8 is changeable,
0079                    bit 9 should be 0 all day. */
0080 #define PVCR_VCSA   (0x1<<14)
0081 #define PVCR_CommandDelay (0xf80)
0082 #define PCFR_PI2C_EN    (0x1 << 6)
0083
0084 #define PSSR_OTGPH  (1 << 6)    /* OTG Peripheral control Hold */
0085 #define PSSR_RDH    (1 << 5)    /* Read Disable Hold */
0086 #define PSSR_PH     (1 << 4)    /* Peripheral Control Hold */
0087 #define PSSR_STS    (1 << 3)    /* Standby Mode Status */
0088 #define PSSR_VFS    (1 << 2)    /* VDD Fault Status */
0089 #define PSSR_BFS    (1 << 1)    /* Battery Fault Status */
0090 #define PSSR_SSS    (1 << 0)    /* Software Sleep Status */
0091
0092 #define PSLR_SL_ROD (1 << 20)   /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
0093
0094 #define PCFR_RO     (1 << 15)   /* RDH Override */
0095 #define PCFR_PO     (1 << 14)   /* PH Override */
0096 #define PCFR_GPROD  (1 << 12)   /* GPIO nRESET_OUT Disable */
0097 #define PCFR_L1_EN  (1 << 11)   /* Sleep Mode L1 converter Enable */
0098 #define PCFR_FVC    (1 << 10)   /* Frequency/Voltage Change */
0099 #define PCFR_DC_EN  (1 << 7)    /* Sleep/deep-sleep DC-DC Converter Enable */
0100 #define PCFR_PI2CEN (1 << 6)    /* Enable PI2C controller */
0101 #define PCFR_GPR_EN (1 << 4)    /* nRESET_GPIO Pin Enable */
0102 #define PCFR_DS     (1 << 3)    /* Deep Sleep Mode */
0103 #define PCFR_FS     (1 << 2)    /* Float Static Chip Selects */
0104 #define PCFR_FP     (1 << 1)    /* Float PCMCIA controls */
0105 #define PCFR_OPDE   (1 << 0)    /* 3.6864 MHz oscillator power-down enable */
0106
0107 #define RCSR_GPR    (1 << 3)    /* GPIO Reset */
0108 #define RCSR_SMR    (1 << 2)    /* Sleep Mode */
0109 #define RCSR_WDR    (1 << 1)    /* Watchdog Reset */
0110 #define RCSR_HWR    (1 << 0)    /* Hardware Reset */
0111
0112 #define PWER_GPIO(Nb)   (1 << Nb)   /* GPIO [0..15] wake-up enable     */
0113 #define PWER_GPIO0  PWER_GPIO (0)   /* GPIO  [0] wake-up enable        */
0114 #define PWER_GPIO1  PWER_GPIO (1)   /* GPIO  [1] wake-up enable        */
0115 #define PWER_GPIO2  PWER_GPIO (2)   /* GPIO  [2] wake-up enable        */
0116 #define PWER_GPIO3  PWER_GPIO (3)   /* GPIO  [3] wake-up enable        */
0117 #define PWER_GPIO4  PWER_GPIO (4)   /* GPIO  [4] wake-up enable        */
0118 #define PWER_GPIO5  PWER_GPIO (5)   /* GPIO  [5] wake-up enable        */
0119 #define PWER_GPIO6  PWER_GPIO (6)   /* GPIO  [6] wake-up enable        */
0120 #define PWER_GPIO7  PWER_GPIO (7)   /* GPIO  [7] wake-up enable        */
0121 #define PWER_GPIO8  PWER_GPIO (8)   /* GPIO  [8] wake-up enable        */
0122 #define PWER_GPIO9  PWER_GPIO (9)   /* GPIO  [9] wake-up enable        */
0123 #define PWER_GPIO10 PWER_GPIO (10)  /* GPIO [10] wake-up enable        */
0124 #define PWER_GPIO11 PWER_GPIO (11)  /* GPIO [11] wake-up enable        */
0125 #define PWER_GPIO12 PWER_GPIO (12)  /* GPIO [12] wake-up enable        */
0126 #define PWER_GPIO13 PWER_GPIO (13)  /* GPIO [13] wake-up enable        */
0127 #define PWER_GPIO14 PWER_GPIO (14)  /* GPIO [14] wake-up enable        */
0128 #define PWER_GPIO15 PWER_GPIO (15)  /* GPIO [15] wake-up enable        */
0129 #define PWER_RTC    0x80000000  /* RTC alarm wake-up enable        */
0130
0131 /*
0132  * PXA2xx specific Core clock definitions
0133  */
0134 #define CCCR        io_p2v(0x41300000)  /* Core Clock Configuration Register */
0135 #define CCSR        io_p2v(0x4130000C)  /* Core Clock Status Register */
0136 #define CKEN        io_p2v(0x41300004)  /* Clock Enable Register */
0137 #define OSCC        io_p2v(0x41300008)  /* Oscillator Configuration Register */
0138
0139 #define OSCC_OON    (1 << 1)    /* 32.768kHz OON (write-once only bit) */
0140 #define OSCC_OOK    (1 << 0)    /* 32.768kHz OOK (read-only bit) */
0141
0142 /* PWRMODE register M field values */
0143
0144 #define PWRMODE_IDLE        0x1
0145 #define PWRMODE_STANDBY     0x2
0146 #define PWRMODE_SLEEP       0x3
0147 #define PWRMODE_DEEPSLEEP   0x7
0148
0149 #endif