arm/mach-pxa/pxa27x-udc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_ARCH_PXA27X_UDC_H
0003 #define _ASM_ARCH_PXA27X_UDC_H
0004
0005 #include "pxa-regs.h"
0006
0007 #ifdef _ASM_ARCH_PXA25X_UDC_H
0008 #error You cannot include both PXA25x and PXA27x UDC support
0009 #endif
0010
0011 #define UDCCR           __REG(0x40600000) /* UDC Control Register */
0012 #define UDCCR_OEN   (1 << 31)   /* On-the-Go Enable */
0013 #define UDCCR_AALTHNP   (1 << 30)   /* A-device Alternate Host Negotiation
0014                        Protocol Port Support */
0015 #define UDCCR_AHNP  (1 << 29)   /* A-device Host Negotiation Protocol
0016                        Support */
0017 #define UDCCR_BHNP  (1 << 28)   /* B-device Host Negotiation Protocol
0018                        Enable */
0019 #define UDCCR_DWRE  (1 << 16)   /* Device Remote Wake-up Enable */
0020 #define UDCCR_ACN   (0x03 << 11)    /* Active UDC configuration Number */
0021 #define UDCCR_ACN_S 11
0022 #define UDCCR_AIN   (0x07 << 8) /* Active UDC interface Number */
0023 #define UDCCR_AIN_S 8
0024 #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
0025                        Setting Number */
0026 #define UDCCR_AAISN_S   5
0027 #define UDCCR_SMAC  (1 << 4)    /* Switch Endpoint Memory to Active
0028                        Configuration */
0029 #define UDCCR_EMCE  (1 << 3)    /* Endpoint Memory Configuration
0030                        Error */
0031 #define UDCCR_UDR   (1 << 2)    /* UDC Resume */
0032 #define UDCCR_UDA   (1 << 1)    /* UDC Active */
0033 #define UDCCR_UDE   (1 << 0)    /* UDC Enable */
0034
0035 #define UDCICR0         __REG(0x40600004) /* UDC Interrupt Control Register0 */
0036 #define UDCICR1         __REG(0x40600008) /* UDC Interrupt Control Register1 */
0037 #define UDCICR_FIFOERR  (1 << 1)    /* FIFO Error interrupt for EP */
0038 #define UDCICR_PKTCOMPL (1 << 0)    /* Packet Complete interrupt for EP */
0039
0040 #define UDC_INT_FIFOERROR  (0x2)
0041 #define UDC_INT_PACKETCMP  (0x1)
0042
0043 #define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
0044 #define UDCICR1_IECC    (1 << 31)   /* IntEn - Configuration Change */
0045 #define UDCICR1_IESOF   (1 << 30)   /* IntEn - Start of Frame */
0046 #define UDCICR1_IERU    (1 << 29)   /* IntEn - Resume */
0047 #define UDCICR1_IESU    (1 << 28)   /* IntEn - Suspend */
0048 #define UDCICR1_IERS    (1 << 27)   /* IntEn - Reset */
0049
0050 #define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
0051 #define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
0052 #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
0053 #define UDCISR1_IRCC    (1 << 31)   /* IntReq - Configuration Change */
0054 #define UDCISR1_IRSOF   (1 << 30)   /* IntReq - Start of Frame */
0055 #define UDCISR1_IRRU    (1 << 29)   /* IntReq - Resume */
0056 #define UDCISR1_IRSU    (1 << 28)   /* IntReq - Suspend */
0057 #define UDCISR1_IRRS    (1 << 27)   /* IntReq - Reset */
0058
0059 #define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
0060 #define UDCOTGICR   __REG(0x40600018) /* UDC On-The-Go interrupt control */
0061 #define UDCOTGICR_IESF  (1 << 24)   /* OTG SET_FEATURE command recvd */
0062 #define UDCOTGICR_IEXR  (1 << 17)   /* Extra Transceiver Interrupt
0063                        Rising Edge Interrupt Enable */
0064 #define UDCOTGICR_IEXF  (1 << 16)   /* Extra Transceiver Interrupt
0065                        Falling Edge Interrupt Enable */
0066 #define UDCOTGICR_IEVV40R (1 << 9)  /* OTG Vbus Valid 4.0V Rising Edge
0067                        Interrupt Enable */
0068 #define UDCOTGICR_IEVV40F (1 << 8)  /* OTG Vbus Valid 4.0V Falling Edge
0069                        Interrupt Enable */
0070 #define UDCOTGICR_IEVV44R (1 << 7)  /* OTG Vbus Valid 4.4V Rising Edge
0071                        Interrupt Enable */
0072 #define UDCOTGICR_IEVV44F (1 << 6)  /* OTG Vbus Valid 4.4V Falling Edge
0073                        Interrupt Enable */
0074 #define UDCOTGICR_IESVR (1 << 5)    /* OTG Session Valid Rising Edge
0075                        Interrupt Enable */
0076 #define UDCOTGICR_IESVF (1 << 4)    /* OTG Session Valid Falling Edge
0077                        Interrupt Enable */
0078 #define UDCOTGICR_IESDR (1 << 3)    /* OTG A-Device SRP Detect Rising
0079                        Edge Interrupt Enable */
0080 #define UDCOTGICR_IESDF (1 << 2)    /* OTG A-Device SRP Detect Falling
0081                        Edge Interrupt Enable */
0082 #define UDCOTGICR_IEIDR (1 << 1)    /* OTG ID Change Rising Edge
0083                        Interrupt Enable */
0084 #define UDCOTGICR_IEIDF (1 << 0)    /* OTG ID Change Falling Edge
0085                        Interrupt Enable */
0086
0087 #define UP2OCR        __REG(0x40600020)  /* USB Port 2 Output Control register */
0088 #define UP3OCR        __REG(0x40600024)  /* USB Port 2 Output Control register */
0089
0090 #define UP2OCR_CPVEN    (1 << 0)    /* Charge Pump Vbus Enable */
0091 #define UP2OCR_CPVPE    (1 << 1)    /* Charge Pump Vbus Pulse Enable */
0092 #define UP2OCR_DPPDE    (1 << 2)    /* Host Port 2 Transceiver D+ Pull Down Enable */
0093 #define UP2OCR_DMPDE    (1 << 3)    /* Host Port 2 Transceiver D- Pull Down Enable */
0094 #define UP2OCR_DPPUE    (1 << 4)    /* Host Port 2 Transceiver D+ Pull Up Enable */
0095 #define UP2OCR_DMPUE    (1 << 5)    /* Host Port 2 Transceiver D- Pull Up Enable */
0096 #define UP2OCR_DPPUBE   (1 << 6)    /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
0097 #define UP2OCR_DMPUBE   (1 << 7)    /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
0098 #define UP2OCR_EXSP     (1 << 8)    /* External Transceiver Speed Control */
0099 #define UP2OCR_EXSUS    (1 << 9)    /* External Transceiver Speed Enable */
0100 #define UP2OCR_IDON     (1 << 10)   /* OTG ID Read Enable */
0101 #define UP2OCR_HXS      (1 << 16)   /* Host Port 2 Transceiver Output Select */
0102 #define UP2OCR_HXOE     (1 << 17)   /* Host Port 2 Transceiver Output Enable */
0103 #define UP2OCR_SEOS(x)      ((x & 7) << 24) /* Single-Ended Output Select */
0104
0105 #define UDCCSN(x)   __REG2(0x40600100, (x) << 2)
0106 #define UDCCSR0         __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
0107 #define UDCCSR0_SA  (1 << 7)    /* Setup Active */
0108 #define UDCCSR0_RNE (1 << 6)    /* Receive FIFO Not Empty */
0109 #define UDCCSR0_FST (1 << 5)    /* Force Stall */
0110 #define UDCCSR0_SST (1 << 4)    /* Sent Stall */
0111 #define UDCCSR0_DME (1 << 3)    /* DMA Enable */
0112 #define UDCCSR0_FTF (1 << 2)    /* Flush Transmit FIFO */
0113 #define UDCCSR0_IPR (1 << 1)    /* IN Packet Ready */
0114 #define UDCCSR0_OPC (1 << 0)    /* OUT Packet Complete */
0115
0116 #define UDCCSRA         __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
0117 #define UDCCSRB         __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
0118 #define UDCCSRC         __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
0119 #define UDCCSRD         __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
0120 #define UDCCSRE         __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
0121 #define UDCCSRF         __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
0122 #define UDCCSRG         __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
0123 #define UDCCSRH         __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
0124 #define UDCCSRI         __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
0125 #define UDCCSRJ         __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
0126 #define UDCCSRK         __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
0127 #define UDCCSRL         __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
0128 #define UDCCSRM         __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
0129 #define UDCCSRN         __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
0130 #define UDCCSRP         __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
0131 #define UDCCSRQ         __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
0132 #define UDCCSRR         __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
0133 #define UDCCSRS         __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
0134 #define UDCCSRT         __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
0135 #define UDCCSRU         __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
0136 #define UDCCSRV         __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
0137 #define UDCCSRW         __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
0138 #define UDCCSRX         __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
0139
0140 #define UDCCSR_DPE  (1 << 9)    /* Data Packet Error */
0141 #define UDCCSR_FEF  (1 << 8)    /* Flush Endpoint FIFO */
0142 #define UDCCSR_SP   (1 << 7)    /* Short Packet Control/Status */
0143 #define UDCCSR_BNE  (1 << 6)    /* Buffer Not Empty (IN endpoints) */
0144 #define UDCCSR_BNF  (1 << 6)    /* Buffer Not Full (OUT endpoints) */
0145 #define UDCCSR_FST  (1 << 5)    /* Force STALL */
0146 #define UDCCSR_SST  (1 << 4)    /* Sent STALL */
0147 #define UDCCSR_DME  (1 << 3)    /* DMA Enable */
0148 #define UDCCSR_TRN  (1 << 2)    /* Tx/Rx NAK */
0149 #define UDCCSR_PC   (1 << 1)    /* Packet Complete */
0150 #define UDCCSR_FS   (1 << 0)    /* FIFO needs service */
0151
0152 #define UDCBCN(x)   __REG2(0x40600200, (x)<<2)
0153 #define UDCBCR0         __REG(0x40600200) /* Byte Count Register - EP0 */
0154 #define UDCBCRA         __REG(0x40600204) /* Byte Count Register - EPA */
0155 #define UDCBCRB         __REG(0x40600208) /* Byte Count Register - EPB */
0156 #define UDCBCRC         __REG(0x4060020C) /* Byte Count Register - EPC */
0157 #define UDCBCRD         __REG(0x40600210) /* Byte Count Register - EPD */
0158 #define UDCBCRE         __REG(0x40600214) /* Byte Count Register - EPE */
0159 #define UDCBCRF         __REG(0x40600218) /* Byte Count Register - EPF */
0160 #define UDCBCRG         __REG(0x4060021C) /* Byte Count Register - EPG */
0161 #define UDCBCRH         __REG(0x40600220) /* Byte Count Register - EPH */
0162 #define UDCBCRI         __REG(0x40600224) /* Byte Count Register - EPI */
0163 #define UDCBCRJ         __REG(0x40600228) /* Byte Count Register - EPJ */
0164 #define UDCBCRK         __REG(0x4060022C) /* Byte Count Register - EPK */
0165 #define UDCBCRL         __REG(0x40600230) /* Byte Count Register - EPL */
0166 #define UDCBCRM         __REG(0x40600234) /* Byte Count Register - EPM */
0167 #define UDCBCRN         __REG(0x40600238) /* Byte Count Register - EPN */
0168 #define UDCBCRP         __REG(0x4060023C) /* Byte Count Register - EPP */
0169 #define UDCBCRQ         __REG(0x40600240) /* Byte Count Register - EPQ */
0170 #define UDCBCRR         __REG(0x40600244) /* Byte Count Register - EPR */
0171 #define UDCBCRS         __REG(0x40600248) /* Byte Count Register - EPS */
0172 #define UDCBCRT         __REG(0x4060024C) /* Byte Count Register - EPT */
0173 #define UDCBCRU         __REG(0x40600250) /* Byte Count Register - EPU */
0174 #define UDCBCRV         __REG(0x40600254) /* Byte Count Register - EPV */
0175 #define UDCBCRW         __REG(0x40600258) /* Byte Count Register - EPW */
0176 #define UDCBCRX         __REG(0x4060025C) /* Byte Count Register - EPX */
0177
0178 #define UDCDN(x)    __REG2(0x40600300, (x)<<2)
0179 #define PHYS_UDCDN(x)   (0x40600300 + ((x)<<2))
0180 #define PUDCDN(x)   (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
0181 #define UDCDR0          __REG(0x40600300) /* Data Register - EP0 */
0182 #define UDCDRA          __REG(0x40600304) /* Data Register - EPA */
0183 #define UDCDRB          __REG(0x40600308) /* Data Register - EPB */
0184 #define UDCDRC          __REG(0x4060030C) /* Data Register - EPC */
0185 #define UDCDRD          __REG(0x40600310) /* Data Register - EPD */
0186 #define UDCDRE          __REG(0x40600314) /* Data Register - EPE */
0187 #define UDCDRF          __REG(0x40600318) /* Data Register - EPF */
0188 #define UDCDRG          __REG(0x4060031C) /* Data Register - EPG */
0189 #define UDCDRH          __REG(0x40600320) /* Data Register - EPH */
0190 #define UDCDRI          __REG(0x40600324) /* Data Register - EPI */
0191 #define UDCDRJ          __REG(0x40600328) /* Data Register - EPJ */
0192 #define UDCDRK          __REG(0x4060032C) /* Data Register - EPK */
0193 #define UDCDRL          __REG(0x40600330) /* Data Register - EPL */
0194 #define UDCDRM          __REG(0x40600334) /* Data Register - EPM */
0195 #define UDCDRN          __REG(0x40600338) /* Data Register - EPN */
0196 #define UDCDRP          __REG(0x4060033C) /* Data Register - EPP */
0197 #define UDCDRQ          __REG(0x40600340) /* Data Register - EPQ */
0198 #define UDCDRR          __REG(0x40600344) /* Data Register - EPR */
0199 #define UDCDRS          __REG(0x40600348) /* Data Register - EPS */
0200 #define UDCDRT          __REG(0x4060034C) /* Data Register - EPT */
0201 #define UDCDRU          __REG(0x40600350) /* Data Register - EPU */
0202 #define UDCDRV          __REG(0x40600354) /* Data Register - EPV */
0203 #define UDCDRW          __REG(0x40600358) /* Data Register - EPW */
0204 #define UDCDRX          __REG(0x4060035C) /* Data Register - EPX */
0205
0206 #define UDCCN(x)       __REG2(0x40600400, (x)<<2)
0207 #define UDCCRA          __REG(0x40600404) /* Configuration register EPA */
0208 #define UDCCRB          __REG(0x40600408) /* Configuration register EPB */
0209 #define UDCCRC          __REG(0x4060040C) /* Configuration register EPC */
0210 #define UDCCRD          __REG(0x40600410) /* Configuration register EPD */
0211 #define UDCCRE          __REG(0x40600414) /* Configuration register EPE */
0212 #define UDCCRF          __REG(0x40600418) /* Configuration register EPF */
0213 #define UDCCRG          __REG(0x4060041C) /* Configuration register EPG */
0214 #define UDCCRH          __REG(0x40600420) /* Configuration register EPH */
0215 #define UDCCRI          __REG(0x40600424) /* Configuration register EPI */
0216 #define UDCCRJ          __REG(0x40600428) /* Configuration register EPJ */
0217 #define UDCCRK          __REG(0x4060042C) /* Configuration register EPK */
0218 #define UDCCRL          __REG(0x40600430) /* Configuration register EPL */
0219 #define UDCCRM          __REG(0x40600434) /* Configuration register EPM */
0220 #define UDCCRN          __REG(0x40600438) /* Configuration register EPN */
0221 #define UDCCRP          __REG(0x4060043C) /* Configuration register EPP */
0222 #define UDCCRQ          __REG(0x40600440) /* Configuration register EPQ */
0223 #define UDCCRR          __REG(0x40600444) /* Configuration register EPR */
0224 #define UDCCRS          __REG(0x40600448) /* Configuration register EPS */
0225 #define UDCCRT          __REG(0x4060044C) /* Configuration register EPT */
0226 #define UDCCRU          __REG(0x40600450) /* Configuration register EPU */
0227 #define UDCCRV          __REG(0x40600454) /* Configuration register EPV */
0228 #define UDCCRW          __REG(0x40600458) /* Configuration register EPW */
0229 #define UDCCRX          __REG(0x4060045C) /* Configuration register EPX */
0230
0231 #define UDCCONR_CN  (0x03 << 25)    /* Configuration Number */
0232 #define UDCCONR_CN_S    (25)
0233 #define UDCCONR_IN  (0x07 << 22)    /* Interface Number */
0234 #define UDCCONR_IN_S    (22)
0235 #define UDCCONR_AISN    (0x07 << 19)    /* Alternate Interface Number */
0236 #define UDCCONR_AISN_S  (19)
0237 #define UDCCONR_EN  (0x0f << 15)    /* Endpoint Number */
0238 #define UDCCONR_EN_S    (15)
0239 #define UDCCONR_ET  (0x03 << 13)    /* Endpoint Type: */
0240 #define UDCCONR_ET_S    (13)
0241 #define UDCCONR_ET_INT  (0x03 << 13)    /*   Interrupt */
0242 #define UDCCONR_ET_BULK (0x02 << 13)    /*   Bulk */
0243 #define UDCCONR_ET_ISO  (0x01 << 13)    /*   Isochronous */
0244 #define UDCCONR_ET_NU   (0x00 << 13)    /*   Not used */
0245 #define UDCCONR_ED  (1 << 12)   /* Endpoint Direction */
0246 #define UDCCONR_MPS (0x3ff << 2)    /* Maximum Packet Size */
0247 #define UDCCONR_MPS_S   (2)
0248 #define UDCCONR_DE  (1 << 1)    /* Double Buffering Enable */
0249 #define UDCCONR_EE  (1 << 0)    /* Endpoint Enable */
0250
0251
0252 #define UDC_INT_FIFOERROR  (0x2)
0253 #define UDC_INT_PACKETCMP  (0x1)
0254
0255 #define UDC_FNR_MASK     (0x7ff)
0256
0257 #define UDCCSR_WR_MASK   (UDCCSR_DME|UDCCSR_FST)
0258 #define UDC_BCR_MASK    (0x3ff)
0259
0260 #endif