arm/mach-pxa/irq.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/arch/arm/mach-pxa/irq.c
0004  *
0005  *  Generic PXA IRQ handling
0006  *
0007  *  Author: Nicolas Pitre
0008  *  Created:    Jun 15, 2001
0009  *  Copyright:  MontaVista Software Inc.
0010  */
0011 #include <linux/bitops.h>
0012 #include <linux/init.h>
0013 #include <linux/module.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/syscore_ops.h>
0016 #include <linux/io.h>
0017 #include <linux/irq.h>
0018 #include <linux/of_address.h>
0019 #include <linux/of_irq.h>
0020 #include <linux/soc/pxa/cpu.h>
0021
0022 #include <asm/exception.h>
0023
0024 #include "irqs.h"
0025
0026 #include "generic.h"
0027 #include "pxa-regs.h"
0028
0029 #define ICIP            (0x000)
0030 #define ICMR            (0x004)
0031 #define ICLR            (0x008)
0032 #define ICFR            (0x00c)
0033 #define ICPR            (0x010)
0034 #define ICCR            (0x014)
0035 #define ICHP            (0x018)
0036 #define IPR(i)          (((i) < 32) ? (0x01c + ((i) << 2)) :        \
0037                 ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) :  \
0038                       (0x144 + (((i) - 64) << 2)))
0039 #define ICHP_VAL_IRQ        (1 << 31)
0040 #define ICHP_IRQ(i)     (((i) >> 16) & 0x7fff)
0041 #define IPR_VALID       (1 << 31)
0042
0043 #define MAX_INTERNAL_IRQS   128
0044
0045 /*
0046  * This is for peripheral IRQs internal to the PXA chip.
0047  */
0048
0049 static void __iomem *pxa_irq_base;
0050 static int pxa_internal_irq_nr;
0051 static bool cpu_has_ipr;
0052 static struct irq_domain *pxa_irq_domain;
0053
0054 static inline void __iomem *irq_base(int i)
0055 {
0056     static unsigned long phys_base_offset[] = {
0057         0x0,
0058         0x9c,
0059         0x130,
0060     };
0061
0062     return pxa_irq_base + phys_base_offset[i];
0063 }
0064
0065 void pxa_mask_irq(struct irq_data *d)
0066 {
0067     void __iomem *base = irq_data_get_irq_chip_data(d);
0068     irq_hw_number_t irq = irqd_to_hwirq(d);
0069     uint32_t icmr = __raw_readl(base + ICMR);
0070
0071     icmr &= ~BIT(irq & 0x1f);
0072     __raw_writel(icmr, base + ICMR);
0073 }
0074
0075 void pxa_unmask_irq(struct irq_data *d)
0076 {
0077     void __iomem *base = irq_data_get_irq_chip_data(d);
0078     irq_hw_number_t irq = irqd_to_hwirq(d);
0079     uint32_t icmr = __raw_readl(base + ICMR);
0080
0081     icmr |= BIT(irq & 0x1f);
0082     __raw_writel(icmr, base + ICMR);
0083 }
0084
0085 static struct irq_chip pxa_internal_irq_chip = {
0086     .name       = "SC",
0087     .irq_ack    = pxa_mask_irq,
0088     .irq_mask   = pxa_mask_irq,
0089     .irq_unmask = pxa_unmask_irq,
0090 };
0091
0092 asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
0093 {
0094     uint32_t icip, icmr, mask;
0095
0096     do {
0097         icip = __raw_readl(pxa_irq_base + ICIP);
0098         icmr = __raw_readl(pxa_irq_base + ICMR);
0099         mask = icip & icmr;
0100
0101         if (mask == 0)
0102             break;
0103
0104         handle_IRQ(PXA_IRQ(fls(mask) - 1), regs);
0105     } while (1);
0106 }
0107
0108 asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
0109 {
0110     uint32_t ichp;
0111
0112     do {
0113         __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp));
0114
0115         if ((ichp & ICHP_VAL_IRQ) == 0)
0116             break;
0117
0118         handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs);
0119     } while (1);
0120 }
0121
0122 static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
0123                irq_hw_number_t hw)
0124 {
0125     void __iomem *base = irq_base(hw / 32);
0126
0127     /* initialize interrupt priority */
0128     if (cpu_has_ipr)
0129         __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
0130
0131     irq_set_chip_and_handler(virq, &pxa_internal_irq_chip,
0132                  handle_level_irq);
0133     irq_set_chip_data(virq, base);
0134
0135     return 0;
0136 }
0137
0138 static const struct irq_domain_ops pxa_irq_ops = {
0139     .map    = pxa_irq_map,
0140     .xlate  = irq_domain_xlate_onecell,
0141 };
0142
0143 static __init void
0144 pxa_init_irq_common(struct device_node *node, int irq_nr,
0145             int (*fn)(struct irq_data *, unsigned int))
0146 {
0147     int n;
0148
0149     pxa_internal_irq_nr = irq_nr;
0150     pxa_irq_domain = irq_domain_add_legacy(node, irq_nr,
0151                            PXA_IRQ(0), 0,
0152                            &pxa_irq_ops, NULL);
0153     if (!pxa_irq_domain)
0154         panic("Unable to add PXA IRQ domain\n");
0155     irq_set_default_host(pxa_irq_domain);
0156
0157     for (n = 0; n < irq_nr; n += 32) {
0158         void __iomem *base = irq_base(n >> 5);
0159
0160         __raw_writel(0, base + ICMR);   /* disable all IRQs */
0161         __raw_writel(0, base + ICLR);   /* all IRQs are IRQ, not FIQ */
0162     }
0163     /* only unmasked interrupts kick us out of idle */
0164     __raw_writel(1, irq_base(0) + ICCR);
0165
0166     pxa_internal_irq_chip.irq_set_wake = fn;
0167 }
0168
0169 void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
0170 {
0171     BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
0172
0173     pxa_irq_base = io_p2v(0x40d00000);
0174     cpu_has_ipr = !cpu_is_pxa25x();
0175     pxa_init_irq_common(NULL, irq_nr, fn);
0176 }
0177
0178 #ifdef CONFIG_PM
0179 static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
0180 static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
0181
0182 static int pxa_irq_suspend(void)
0183 {
0184     int i;
0185
0186     for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) {
0187         void __iomem *base = irq_base(i);
0188
0189         saved_icmr[i] = __raw_readl(base + ICMR);
0190         __raw_writel(0, base + ICMR);
0191     }
0192
0193     if (cpu_has_ipr) {
0194         for (i = 0; i < pxa_internal_irq_nr; i++)
0195             saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i));
0196     }
0197
0198     return 0;
0199 }
0200
0201 static void pxa_irq_resume(void)
0202 {
0203     int i;
0204
0205     for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) {
0206         void __iomem *base = irq_base(i);
0207
0208         __raw_writel(saved_icmr[i], base + ICMR);
0209         __raw_writel(0, base + ICLR);
0210     }
0211
0212     if (cpu_has_ipr)
0213         for (i = 0; i < pxa_internal_irq_nr; i++)
0214             __raw_writel(saved_ipr[i], pxa_irq_base + IPR(i));
0215
0216     __raw_writel(1, pxa_irq_base + ICCR);
0217 }
0218 #else
0219 #define pxa_irq_suspend     NULL
0220 #define pxa_irq_resume      NULL
0221 #endif
0222
0223 struct syscore_ops pxa_irq_syscore_ops = {
0224     .suspend    = pxa_irq_suspend,
0225     .resume     = pxa_irq_resume,
0226 };
0227
0228 #ifdef CONFIG_OF
0229 static const struct of_device_id intc_ids[] __initconst = {
0230     { .compatible = "marvell,pxa-intc", },
0231     {}
0232 };
0233
0234 void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
0235 {
0236     struct device_node *node;
0237     struct resource res;
0238     int ret;
0239
0240     node = of_find_matching_node(NULL, intc_ids);
0241     if (!node) {
0242         pr_err("Failed to find interrupt controller in arch-pxa\n");
0243         return;
0244     }
0245
0246     ret = of_property_read_u32(node, "marvell,intc-nr-irqs",
0247                    &pxa_internal_irq_nr);
0248     if (ret) {
0249         pr_err("Not found marvell,intc-nr-irqs property\n");
0250         return;
0251     }
0252
0253     ret = of_address_to_resource(node, 0, &res);
0254     if (ret < 0) {
0255         pr_err("No registers defined for node\n");
0256         return;
0257     }
0258     pxa_irq_base = io_p2v(res.start);
0259
0260     if (of_find_property(node, "marvell,intc-priority", NULL))
0261         cpu_has_ipr = 1;
0262
0263     ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0);
0264     if (ret < 0) {
0265         pr_err("Failed to allocate IRQ numbers\n");
0266         return;
0267     }
0268
0269     pxa_init_irq_common(node, pxa_internal_irq_nr, fn);
0270 }
0271 #endif /* CONFIG_OF */