arm/mach-pxa/idp.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  arch/arm/mach-pxa/include/mach/idp.h
0004  *
0005  * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
0006  *
0007  * 2001-09-13: Cliff Brake <cbrake@accelent.com>
0008  *             Initial code
0009  *
0010  * 2005-02-15: Cliff Brake <cliff.brake@gmail.com>
0011  *             <http://www.vibren.com> <http://bec-systems.com>
0012  *             Changes for 2.6 kernel.
0013  */
0014
0015
0016 /*
0017  * Note: this file must be safe to include in assembly files
0018  *
0019  * Support for the Vibren PXA255 IDP requires rev04 or later
0020  * IDP hardware.
0021  */
0022
0023 #include "irqs.h" /* PXA_GPIO_TO_IRQ */
0024
0025 #define IDP_FLASH_PHYS      (PXA_CS0_PHYS)
0026 #define IDP_ALT_FLASH_PHYS  (PXA_CS1_PHYS)
0027 #define IDP_MEDIAQ_PHYS     (PXA_CS3_PHYS)
0028 #define IDP_IDE_PHYS        (PXA_CS5_PHYS + 0x03000000)
0029 #define IDP_ETH_PHYS        (PXA_CS5_PHYS + 0x03400000)
0030 #define IDP_COREVOLT_PHYS   (PXA_CS5_PHYS + 0x03800000)
0031 #define IDP_CPLD_PHYS       (PXA_CS5_PHYS + 0x03C00000)
0032
0033
0034 /*
0035  * virtual memory map
0036  */
0037
0038 #define IDP_COREVOLT_VIRT   (0xf0000000)
0039 #define IDP_COREVOLT_SIZE   (1*1024*1024)
0040
0041 #define IDP_CPLD_VIRT       (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE)
0042 #define IDP_CPLD_SIZE       (1*1024*1024)
0043
0044 #if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000
0045 #error Your custom IO space is getting a bit large !!
0046 #endif
0047
0048 #define CPLD_P2V(x)     ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT)
0049 #define CPLD_V2P(x)     ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS)
0050
0051 #ifndef __ASSEMBLY__
0052 #  define __CPLD_REG(x)     (*((volatile unsigned long *)CPLD_P2V(x)))
0053 #else
0054 #  define __CPLD_REG(x)     CPLD_P2V(x)
0055 #endif
0056
0057 /* board level registers in the CPLD: (offsets from CPLD_VIRT) */
0058
0059 #define _IDP_CPLD_REV           (IDP_CPLD_PHYS + 0x00)
0060 #define _IDP_CPLD_PERIPH_PWR        (IDP_CPLD_PHYS + 0x04)
0061 #define _IDP_CPLD_LED_CONTROL       (IDP_CPLD_PHYS + 0x08)
0062 #define _IDP_CPLD_KB_COL_HIGH       (IDP_CPLD_PHYS + 0x0C)
0063 #define _IDP_CPLD_KB_COL_LOW        (IDP_CPLD_PHYS + 0x10)
0064 #define _IDP_CPLD_PCCARD_EN     (IDP_CPLD_PHYS + 0x14)
0065 #define _IDP_CPLD_GPIOH_DIR     (IDP_CPLD_PHYS + 0x18)
0066 #define _IDP_CPLD_GPIOH_VALUE       (IDP_CPLD_PHYS + 0x1C)
0067 #define _IDP_CPLD_GPIOL_DIR     (IDP_CPLD_PHYS + 0x20)
0068 #define _IDP_CPLD_GPIOL_VALUE       (IDP_CPLD_PHYS + 0x24)
0069 #define _IDP_CPLD_PCCARD_PWR        (IDP_CPLD_PHYS + 0x28)
0070 #define _IDP_CPLD_MISC_CTRL     (IDP_CPLD_PHYS + 0x2C)
0071 #define _IDP_CPLD_LCD           (IDP_CPLD_PHYS + 0x30)
0072 #define _IDP_CPLD_FLASH_WE      (IDP_CPLD_PHYS + 0x34)
0073
0074 #define _IDP_CPLD_KB_ROW        (IDP_CPLD_PHYS + 0x50)
0075 #define _IDP_CPLD_PCCARD0_STATUS    (IDP_CPLD_PHYS + 0x54)
0076 #define _IDP_CPLD_PCCARD1_STATUS    (IDP_CPLD_PHYS + 0x58)
0077 #define _IDP_CPLD_MISC_STATUS       (IDP_CPLD_PHYS + 0x5C)
0078
0079 /* FPGA register virtual addresses */
0080
0081 #define IDP_CPLD_REV            __CPLD_REG(_IDP_CPLD_REV)
0082 #define IDP_CPLD_PERIPH_PWR     __CPLD_REG(_IDP_CPLD_PERIPH_PWR)
0083 #define IDP_CPLD_LED_CONTROL        __CPLD_REG(_IDP_CPLD_LED_CONTROL)
0084 #define IDP_CPLD_KB_COL_HIGH        __CPLD_REG(_IDP_CPLD_KB_COL_HIGH)
0085 #define IDP_CPLD_KB_COL_LOW     __CPLD_REG(_IDP_CPLD_KB_COL_LOW)
0086 #define IDP_CPLD_PCCARD_EN      __CPLD_REG(_IDP_CPLD_PCCARD_EN)
0087 #define IDP_CPLD_GPIOH_DIR      __CPLD_REG(_IDP_CPLD_GPIOH_DIR)
0088 #define IDP_CPLD_GPIOH_VALUE        __CPLD_REG(_IDP_CPLD_GPIOH_VALUE)
0089 #define IDP_CPLD_GPIOL_DIR      __CPLD_REG(_IDP_CPLD_GPIOL_DIR)
0090 #define IDP_CPLD_GPIOL_VALUE        __CPLD_REG(_IDP_CPLD_GPIOL_VALUE)
0091 #define IDP_CPLD_PCCARD_PWR     __CPLD_REG(_IDP_CPLD_PCCARD_PWR)
0092 #define IDP_CPLD_MISC_CTRL      __CPLD_REG(_IDP_CPLD_MISC_CTRL)
0093 #define IDP_CPLD_LCD            __CPLD_REG(_IDP_CPLD_LCD)
0094 #define IDP_CPLD_FLASH_WE       __CPLD_REG(_IDP_CPLD_FLASH_WE)
0095
0096 #define IDP_CPLD_KB_ROW             __CPLD_REG(_IDP_CPLD_KB_ROW)
0097 #define IDP_CPLD_PCCARD0_STATUS         __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS)
0098 #define IDP_CPLD_PCCARD1_STATUS         __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS)
0099 #define IDP_CPLD_MISC_STATUS        __CPLD_REG(_IDP_CPLD_MISC_STATUS)
0100
0101
0102 /*
0103  * Bit masks for various registers
0104  */
0105
0106 // IDP_CPLD_PCCARD_PWR
0107 #define PCC0_PWR0   (1 << 0)
0108 #define PCC0_PWR1   (1 << 1)
0109 #define PCC0_PWR2   (1 << 2)
0110 #define PCC0_PWR3   (1 << 3)
0111 #define PCC1_PWR0   (1 << 4)
0112 #define PCC1_PWR1   (1 << 5)
0113 #define PCC1_PWR2   (1 << 6)
0114 #define PCC1_PWR3   (1 << 7)
0115
0116 // IDP_CPLD_PCCARD_EN
0117 #define PCC0_RESET  (1 << 6)
0118 #define PCC1_RESET  (1 << 7)
0119 #define PCC0_ENABLE (1 << 0)
0120 #define PCC1_ENABLE (1 << 1)
0121
0122 // IDP_CPLD_PCCARDx_STATUS
0123 #define _PCC_WRPROT (1 << 7) // 7-4 read as low true
0124 #define _PCC_RESET  (1 << 6)
0125 #define _PCC_IRQ    (1 << 5)
0126 #define _PCC_INPACK (1 << 4)
0127 #define PCC_BVD2    (1 << 3)
0128 #define PCC_BVD1    (1 << 2)
0129 #define PCC_VS2     (1 << 1)
0130 #define PCC_VS1     (1 << 0)
0131
0132 /* A listing of interrupts used by external hardware devices */
0133
0134 #define TOUCH_PANEL_IRQ         PXA_GPIO_TO_IRQ(5)
0135 #define IDE_IRQ             PXA_GPIO_TO_IRQ(21)
0136
0137 #define TOUCH_PANEL_IRQ_EDGE        IRQ_TYPE_EDGE_FALLING
0138
0139 #define ETHERNET_IRQ            PXA_GPIO_TO_IRQ(4)
0140 #define ETHERNET_IRQ_EDGE       IRQ_TYPE_EDGE_RISING
0141
0142 #define IDE_IRQ_EDGE            IRQ_TYPE_EDGE_RISING
0143
0144 #define PCMCIA_S0_CD_VALID      PXA_GPIO_TO_IRQ(7)
0145 #define PCMCIA_S0_CD_VALID_EDGE     IRQ_TYPE_EDGE_BOTH
0146
0147 #define PCMCIA_S1_CD_VALID      PXA_GPIO_TO_IRQ(8)
0148 #define PCMCIA_S1_CD_VALID_EDGE     IRQ_TYPE_EDGE_BOTH
0149
0150 #define PCMCIA_S0_RDYINT        PXA_GPIO_TO_IRQ(19)
0151 #define PCMCIA_S1_RDYINT        PXA_GPIO_TO_IRQ(22)
0152
0153
0154 /*
0155  * Macros for LED Driver
0156  */
0157
0158 /* leds 0 = ON */
0159 #define IDP_HB_LED  (1<<5)
0160 #define IDP_BUSY_LED    (1<<6)
0161
0162 #define IDP_LEDS_MASK   (IDP_HB_LED | IDP_BUSY_LED)
0163
0164 /*
0165  * macros for MTD driver
0166  */
0167
0168 #define FLASH_WRITE_PROTECT_DISABLE()   ((IDP_CPLD_FLASH_WE) &= ~(0x1))
0169 #define FLASH_WRITE_PROTECT_ENABLE()    ((IDP_CPLD_FLASH_WE) |= (0x1))
0170
0171 /*
0172  * macros for matrix keyboard driver
0173  */
0174
0175 #define KEYBD_MATRIX_NUMBER_INPUTS  7
0176 #define KEYBD_MATRIX_NUMBER_OUTPUTS 14
0177
0178 #define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC    FALSE
0179 #define KEYBD_MATRIX_INVERT_INPUT_LOGIC     FALSE
0180
0181 #define KEYBD_MATRIX_SETTLING_TIME_US           100
0182 #define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT     2
0183
0184 #define KEYBD_MATRIX_SET_OUTPUTS(outputs) \
0185 {\
0186     IDP_CPLD_KB_COL_LOW = outputs;\
0187     IDP_CPLD_KB_COL_HIGH = outputs >> 7;\
0188 }
0189
0190 #define KEYBD_MATRIX_GET_INPUTS(inputs) \
0191 {\
0192     inputs = (IDP_CPLD_KB_ROW & 0x7f);\
0193 }
0194
0195