arm/mach-pxa/generic.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/arch/arm/mach-pxa/generic.c
0004  *
0005  *  Author: Nicolas Pitre
0006  *  Created:    Jun 15, 2001
0007  *  Copyright:  MontaVista Software Inc.
0008  *
0009  * Code common to all PXA machines.
0010  *
0011  * Since this file should be linked before any other machine specific file,
0012  * the __initcall() here will be executed first.  This serves as default
0013  * initialization stuff for PXA machines which can be overridden later if
0014  * need be.
0015  */
0016 #include <linux/gpio.h>
0017 #include <linux/module.h>
0018 #include <linux/kernel.h>
0019 #include <linux/init.h>
0020 #include <linux/soc/pxa/cpu.h>
0021 #include <linux/soc/pxa/smemc.h>
0022 #include <linux/clk/pxa.h>
0023
0024 #include <asm/mach/map.h>
0025 #include <asm/mach-types.h>
0026
0027 #include "addr-map.h"
0028 #include "irqs.h"
0029 #include "reset.h"
0030 #include "smemc.h"
0031 #include "pxa3xx-regs.h"
0032
0033 #include "generic.h"
0034 #include <clocksource/pxa.h>
0035
0036 void clear_reset_status(unsigned int mask)
0037 {
0038     if (cpu_is_pxa2xx())
0039         pxa2xx_clear_reset_status(mask);
0040     else {
0041         /* RESET_STATUS_* has a 1:1 mapping with ARSR */
0042         ARSR = mask;
0043     }
0044 }
0045
0046 /*
0047  * For non device-tree builds, keep legacy timer init
0048  */
0049 void __init pxa_timer_init(void)
0050 {
0051     if (cpu_is_pxa25x())
0052         pxa25x_clocks_init(io_p2v(0x41300000));
0053     if (cpu_is_pxa27x())
0054         pxa27x_clocks_init(io_p2v(0x41300000));
0055     if (cpu_is_pxa3xx())
0056         pxa3xx_clocks_init(io_p2v(0x41340000), io_p2v(0x41350000));
0057     pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000));
0058 }
0059
0060 void pxa_smemc_set_pcmcia_timing(int sock, u32 mcmem, u32 mcatt, u32 mcio)
0061 {
0062     __raw_writel(mcmem, MCMEM(sock));
0063     __raw_writel(mcatt, MCATT(sock));
0064     __raw_writel(mcio, MCIO(sock));
0065 }
0066 EXPORT_SYMBOL_GPL(pxa_smemc_set_pcmcia_timing);
0067
0068 void pxa_smemc_set_pcmcia_socket(int nr)
0069 {
0070     switch (nr) {
0071     case 0:
0072         __raw_writel(0, MECR);
0073         break;
0074     case 1:
0075         /*
0076          * We have at least one socket, so set MECR:CIT
0077          * (Card Is There)
0078          */
0079         __raw_writel(MECR_CIT, MECR);
0080         break;
0081     case 2:
0082         /* Set CIT and MECR:NOS (Number Of Sockets) */
0083         __raw_writel(MECR_CIT | MECR_NOS, MECR);
0084         break;
0085     }
0086 }
0087 EXPORT_SYMBOL_GPL(pxa_smemc_set_pcmcia_socket);
0088
0089 void __iomem *pxa_smemc_get_mdrefr(void)
0090 {
0091     return MDREFR;
0092 }
0093
0094 /*
0095  * Intel PXA2xx internal register mapping.
0096  *
0097  * Note: virtual 0xfffe0000-0xffffffff is reserved for the vector table
0098  *       and cache flush area.
0099  */
0100 static struct map_desc common_io_desc[] __initdata = {
0101     {   /* Devs */
0102         .virtual    = (unsigned long)PERIPH_VIRT,
0103         .pfn        = __phys_to_pfn(PERIPH_PHYS),
0104         .length     = PERIPH_SIZE,
0105         .type       = MT_DEVICE
0106     }
0107 };
0108
0109 void __init pxa_map_io(void)
0110 {
0111     debug_ll_io_init();
0112     iotable_init(ARRAY_AND_SIZE(common_io_desc));
0113 }