arm/mach-pxa/addr-map.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ASM_MACH_ADDR_MAP_H
0003 #define __ASM_MACH_ADDR_MAP_H
0004
0005 /*
0006  * Chip Selects
0007  */
0008 #define PXA_CS0_PHYS        0x00000000
0009 #define PXA_CS1_PHYS        0x04000000
0010 #define PXA_CS2_PHYS        0x08000000
0011 #define PXA_CS3_PHYS        0x0C000000
0012 #define PXA_CS4_PHYS        0x10000000
0013 #define PXA_CS5_PHYS        0x14000000
0014
0015 #define PXA300_CS0_PHYS     0x00000000  /* PXA300/PXA310 _only_ */
0016 #define PXA300_CS1_PHYS     0x30000000  /* PXA300/PXA310 _only_ */
0017 #define PXA3xx_CS2_PHYS     0x10000000
0018 #define PXA3xx_CS3_PHYS     0x14000000
0019
0020 /*
0021  * Peripheral Bus
0022  */
0023 #define PERIPH_PHYS     0x40000000
0024 #define PERIPH_VIRT     IOMEM(0xf2000000)
0025 #define PERIPH_SIZE     0x02000000
0026
0027 /*
0028  * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x)
0029  */
0030 #define PXA2XX_SMEMC_PHYS   0x48000000
0031 #define PXA3XX_SMEMC_PHYS   0x4a000000
0032 #define SMEMC_VIRT      IOMEM(0xf6000000)
0033 #define SMEMC_SIZE      0x00100000
0034
0035 /*
0036  * Dynamic Memory Controller (only on PXA3xx)
0037  */
0038 #define DMEMC_PHYS      0x48100000
0039 #define DMEMC_VIRT      IOMEM(0xf6100000)
0040 #define DMEMC_SIZE      0x00100000
0041
0042 /*
0043  * Reserved space for low level debug virtual addresses within
0044  * 0xf6200000..0xf6201000
0045  */
0046
0047 /*
0048  * DFI Bus for NAND, PXA3xx only
0049  */
0050 #define NAND_PHYS       0x43100000
0051 #define NAND_VIRT       IOMEM(0xf6300000)
0052 #define NAND_SIZE       0x00100000
0053
0054 /*
0055  * Internal Memory Controller (PXA27x and later)
0056  */
0057 #define IMEMC_PHYS      0x58000000
0058 #define IMEMC_VIRT      IOMEM(0xfe000000)
0059 #define IMEMC_SIZE      0x00100000
0060
0061 #endif /* __ASM_MACH_ADDR_MAP_H */