arm/mach-oxnas/platsmp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
0004  * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
0005  * Copyright (C) 2002 ARM Ltd.
0006  * All Rights Reserved
0007  */
0008 #include <linux/io.h>
0009 #include <linux/delay.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012
0013 #include <asm/cacheflush.h>
0014 #include <asm/cp15.h>
0015 #include <asm/smp_plat.h>
0016 #include <asm/smp_scu.h>
0017
0018 extern void ox820_secondary_startup(void);
0019
0020 static void __iomem *cpu_ctrl;
0021 static void __iomem *gic_cpu_ctrl;
0022
0023 #define HOLDINGPEN_CPU_OFFSET       0xc8
0024 #define HOLDINGPEN_LOCATION_OFFSET  0xc4
0025
0026 #define GIC_NCPU_OFFSET(cpu)        (0x100 + (cpu)*0x100)
0027 #define GIC_CPU_CTRL            0x00
0028 #define GIC_CPU_CTRL_ENABLE     1
0029
0030 static int __init ox820_boot_secondary(unsigned int cpu,
0031         struct task_struct *idle)
0032 {
0033     /*
0034      * Write the address of secondary startup into the
0035      * system-wide flags register. The BootMonitor waits
0036      * until it receives a soft interrupt, and then the
0037      * secondary CPU branches to this address.
0038      */
0039     writel(virt_to_phys(ox820_secondary_startup),
0040             cpu_ctrl + HOLDINGPEN_LOCATION_OFFSET);
0041
0042     writel(cpu, cpu_ctrl + HOLDINGPEN_CPU_OFFSET);
0043
0044     /*
0045      * Enable GIC cpu interface in CPU Interface Control Register
0046      */
0047     writel(GIC_CPU_CTRL_ENABLE,
0048         gic_cpu_ctrl + GIC_NCPU_OFFSET(cpu) + GIC_CPU_CTRL);
0049
0050     /*
0051      * Send the secondary CPU a soft interrupt, thereby causing
0052      * the boot monitor to read the system wide flags register,
0053      * and branch to the address found there.
0054      */
0055     arch_send_wakeup_ipi_mask(cpumask_of(cpu));
0056
0057     return 0;
0058 }
0059
0060 static void __init ox820_smp_prepare_cpus(unsigned int max_cpus)
0061 {
0062     struct device_node *np;
0063     void __iomem *scu_base;
0064
0065     np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-scu");
0066     scu_base = of_iomap(np, 0);
0067     of_node_put(np);
0068     if (!scu_base)
0069         return;
0070
0071     /* Remap CPU Interrupt Interface Registers */
0072     np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-gic");
0073     gic_cpu_ctrl = of_iomap(np, 1);
0074     of_node_put(np);
0075     if (!gic_cpu_ctrl)
0076         goto unmap_scu;
0077
0078     np = of_find_compatible_node(NULL, NULL, "oxsemi,ox820-sys-ctrl");
0079     cpu_ctrl = of_iomap(np, 0);
0080     of_node_put(np);
0081     if (!cpu_ctrl)
0082         goto unmap_scu;
0083
0084     scu_enable(scu_base);
0085     flush_cache_all();
0086
0087 unmap_scu:
0088     iounmap(scu_base);
0089 }
0090
0091 static const struct smp_operations ox820_smp_ops __initconst = {
0092     .smp_prepare_cpus   = ox820_smp_prepare_cpus,
0093     .smp_boot_secondary = ox820_boot_secondary,
0094 };
0095
0096 CPU_METHOD_OF_DECLARE(ox820_smp, "oxsemi,ox820-smp", &ox820_smp_ops);