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0009 #include <linux/gpio.h>
0010 #include <linux/kernel.h>
0011 #include <linux/init.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/pci.h>
0014 #include <linux/irq.h>
0015 #include <linux/mtd/physmap.h>
0016 #include <linux/mv643xx_eth.h>
0017 #include <linux/ata_platform.h>
0018 #include <linux/i2c.h>
0019 #include <linux/leds.h>
0020 #include <asm/mach-types.h>
0021 #include <asm/mach/arch.h>
0022 #include <asm/mach/pci.h>
0023 #include "common.h"
0024 #include "mpp.h"
0025 #include "orion5x.h"
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035 #define RD88F5182_NOR_BOOT_BASE 0xf4000000
0036 #define RD88F5182_NOR_BOOT_SIZE SZ_512K
0037
0038
0039
0040
0041
0042 #define RD88F5182_NOR_BASE 0xfc000000
0043 #define RD88F5182_NOR_SIZE SZ_16M
0044
0045
0046
0047
0048
0049 #define RD88F5182_PCI_SLOT0_OFFS 7
0050 #define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
0051 #define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
0052
0053
0054
0055
0056
0057 static struct physmap_flash_data rd88f5182_nor_flash_data = {
0058 .width = 1,
0059 };
0060
0061 static struct resource rd88f5182_nor_flash_resource = {
0062 .flags = IORESOURCE_MEM,
0063 .start = RD88F5182_NOR_BASE,
0064 .end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
0065 };
0066
0067 static struct platform_device rd88f5182_nor_flash = {
0068 .name = "physmap-flash",
0069 .id = 0,
0070 .dev = {
0071 .platform_data = &rd88f5182_nor_flash_data,
0072 },
0073 .num_resources = 1,
0074 .resource = &rd88f5182_nor_flash_resource,
0075 };
0076
0077
0078
0079
0080
0081 #define RD88F5182_GPIO_LED 0
0082
0083 static struct gpio_led rd88f5182_gpio_led_pins[] = {
0084 {
0085 .name = "rd88f5182:cpu",
0086 .default_trigger = "cpu0",
0087 .gpio = RD88F5182_GPIO_LED,
0088 },
0089 };
0090
0091 static struct gpio_led_platform_data rd88f5182_gpio_led_data = {
0092 .leds = rd88f5182_gpio_led_pins,
0093 .num_leds = ARRAY_SIZE(rd88f5182_gpio_led_pins),
0094 };
0095
0096 static struct platform_device rd88f5182_gpio_leds = {
0097 .name = "leds-gpio",
0098 .id = -1,
0099 .dev = {
0100 .platform_data = &rd88f5182_gpio_led_data,
0101 },
0102 };
0103
0104
0105
0106
0107
0108 static void __init rd88f5182_pci_preinit(void)
0109 {
0110 int pin;
0111
0112
0113
0114
0115 pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
0116 if (gpio_request(pin, "PCI IntA") == 0) {
0117 if (gpio_direction_input(pin) == 0) {
0118 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
0119 } else {
0120 printk(KERN_ERR "rd88f5182_pci_preinit failed to "
0121 "set_irq_type pin %d\n", pin);
0122 gpio_free(pin);
0123 }
0124 } else {
0125 printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
0126 }
0127
0128 pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
0129 if (gpio_request(pin, "PCI IntB") == 0) {
0130 if (gpio_direction_input(pin) == 0) {
0131 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
0132 } else {
0133 printk(KERN_ERR "rd88f5182_pci_preinit failed to "
0134 "set_irq_type pin %d\n", pin);
0135 gpio_free(pin);
0136 }
0137 } else {
0138 printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
0139 }
0140 }
0141
0142 static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
0143 u8 pin)
0144 {
0145 int irq;
0146
0147
0148
0149
0150 irq = orion5x_pci_map_irq(dev, slot, pin);
0151 if (irq != -1)
0152 return irq;
0153
0154
0155
0156
0157 switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
0158 case 0:
0159 if (pin == 1)
0160 return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
0161 else
0162 return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
0163 default:
0164 return -1;
0165 }
0166 }
0167
0168 static struct hw_pci rd88f5182_pci __initdata = {
0169 .nr_controllers = 2,
0170 .preinit = rd88f5182_pci_preinit,
0171 .setup = orion5x_pci_sys_setup,
0172 .scan = orion5x_pci_sys_scan_bus,
0173 .map_irq = rd88f5182_pci_map_irq,
0174 };
0175
0176 static int __init rd88f5182_pci_init(void)
0177 {
0178 if (machine_is_rd88f5182())
0179 pci_common_init(&rd88f5182_pci);
0180
0181 return 0;
0182 }
0183
0184 subsys_initcall(rd88f5182_pci_init);
0185
0186
0187
0188
0189
0190 static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
0191 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
0192 };
0193
0194
0195
0196
0197 static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
0198 I2C_BOARD_INFO("ds1338", 0x68),
0199 };
0200
0201
0202
0203
0204 static struct mv_sata_platform_data rd88f5182_sata_data = {
0205 .n_ports = 2,
0206 };
0207
0208
0209
0210
0211 static unsigned int rd88f5182_mpp_modes[] __initdata = {
0212 MPP0_GPIO,
0213 MPP1_GPIO,
0214 MPP2_UNUSED,
0215 MPP3_GPIO,
0216 MPP4_GPIO,
0217 MPP5_GPIO,
0218 MPP6_GPIO,
0219 MPP7_GPIO,
0220 MPP8_UNUSED,
0221 MPP9_UNUSED,
0222 MPP10_UNUSED,
0223 MPP11_UNUSED,
0224 MPP12_SATA_LED,
0225 MPP13_SATA_LED,
0226 MPP14_SATA_LED,
0227 MPP15_SATA_LED,
0228 MPP16_UNUSED,
0229 MPP17_UNUSED,
0230 MPP18_UNUSED,
0231 MPP19_UNUSED,
0232 0,
0233 };
0234
0235 static void __init rd88f5182_init(void)
0236 {
0237
0238
0239
0240 orion5x_init();
0241
0242 orion5x_mpp_conf(rd88f5182_mpp_modes);
0243
0244
0245
0246
0247
0248
0249
0250
0251
0252
0253
0254
0255
0256 orion5x_ehci0_init();
0257 orion5x_ehci1_init();
0258 orion5x_eth_init(&rd88f5182_eth_data);
0259 orion5x_i2c_init();
0260 orion5x_sata_init(&rd88f5182_sata_data);
0261 orion5x_uart0_init();
0262 orion5x_xor_init();
0263
0264 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
0265 ORION_MBUS_DEVBUS_BOOT_ATTR,
0266 RD88F5182_NOR_BOOT_BASE,
0267 RD88F5182_NOR_BOOT_SIZE);
0268 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
0269 ORION_MBUS_DEVBUS_ATTR(1),
0270 RD88F5182_NOR_BASE,
0271 RD88F5182_NOR_SIZE);
0272 platform_device_register(&rd88f5182_nor_flash);
0273 platform_device_register(&rd88f5182_gpio_leds);
0274
0275 i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
0276 }
0277
0278 MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
0279
0280 .atag_offset = 0x100,
0281 .nr_irqs = ORION5X_NR_IRQS,
0282 .init_machine = rd88f5182_init,
0283 .map_io = orion5x_map_io,
0284 .init_early = orion5x_init_early,
0285 .init_irq = orion5x_init_irq,
0286 .init_time = orion5x_timer_init,
0287 .restart = orion5x_restart,
0288 MACHINE_END