arm/mach-orion5x/pci.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * arch/arm/mach-orion5x/pci.c
0004  *
0005  * PCI and PCIe functions for Marvell Orion System On Chip
0006  *
0007  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
0008  */
0009
0010 #include <linux/kernel.h>
0011 #include <linux/pci.h>
0012 #include <linux/slab.h>
0013 #include <linux/mbus.h>
0014 #include <video/vga.h>
0015 #include <asm/irq.h>
0016 #include <asm/mach/pci.h>
0017 #include <plat/pcie.h>
0018 #include <plat/addr-map.h>
0019 #include "common.h"
0020 #include "orion5x.h"
0021
0022 /*****************************************************************************
0023  * Orion has one PCIe controller and one PCI controller.
0024  *
0025  * Note1: The local PCIe bus number is '0'. The local PCI bus number
0026  * follows the scanned PCIe bridged busses, if any.
0027  *
0028  * Note2: It is possible for PCI/PCIe agents to access many subsystem's
0029  * space, by configuring BARs and Address Decode Windows, e.g. flashes on
0030  * device bus, Orion registers, etc. However this code only enable the
0031  * access to DDR banks.
0032  ****************************************************************************/
0033
0034
0035 /*****************************************************************************
0036  * PCIe controller
0037  ****************************************************************************/
0038 #define PCIE_BASE   (ORION5X_PCIE_VIRT_BASE)
0039
0040 void __init orion5x_pcie_id(u32 *dev, u32 *rev)
0041 {
0042     *dev = orion_pcie_dev_id(PCIE_BASE);
0043     *rev = orion_pcie_rev(PCIE_BASE);
0044 }
0045
0046 static int pcie_valid_config(int bus, int dev)
0047 {
0048     /*
0049      * Don't go out when trying to access --
0050      * 1. nonexisting device on local bus
0051      * 2. where there's no device connected (no link)
0052      */
0053     if (bus == 0 && dev == 0)
0054         return 1;
0055
0056     if (!orion_pcie_link_up(PCIE_BASE))
0057         return 0;
0058
0059     if (bus == 0 && dev != 1)
0060         return 0;
0061
0062     return 1;
0063 }
0064
0065
0066 /*
0067  * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
0068  * and then reading the PCIE_CONF_DATA register. Need to make sure these
0069  * transactions are atomic.
0070  */
0071 static DEFINE_SPINLOCK(orion5x_pcie_lock);
0072
0073 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
0074             int size, u32 *val)
0075 {
0076     unsigned long flags;
0077     int ret;
0078
0079     if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
0080         *val = 0xffffffff;
0081         return PCIBIOS_DEVICE_NOT_FOUND;
0082     }
0083
0084     spin_lock_irqsave(&orion5x_pcie_lock, flags);
0085     ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
0086     spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
0087
0088     return ret;
0089 }
0090
0091 static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
0092                int where, int size, u32 *val)
0093 {
0094     int ret;
0095
0096     if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
0097         *val = 0xffffffff;
0098         return PCIBIOS_DEVICE_NOT_FOUND;
0099     }
0100
0101     /*
0102      * We only support access to the non-extended configuration
0103      * space when using the WA access method (or we would have to
0104      * sacrifice 256M of CPU virtual address space.)
0105      */
0106     if (where >= 0x100) {
0107         *val = 0xffffffff;
0108         return PCIBIOS_DEVICE_NOT_FOUND;
0109     }
0110
0111     ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
0112                     bus, devfn, where, size, val);
0113
0114     return ret;
0115 }
0116
0117 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
0118             int where, int size, u32 val)
0119 {
0120     unsigned long flags;
0121     int ret;
0122
0123     if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
0124         return PCIBIOS_DEVICE_NOT_FOUND;
0125
0126     spin_lock_irqsave(&orion5x_pcie_lock, flags);
0127     ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
0128     spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
0129
0130     return ret;
0131 }
0132
0133 static struct pci_ops pcie_ops = {
0134     .read = pcie_rd_conf,
0135     .write = pcie_wr_conf,
0136 };
0137
0138
0139 static int __init pcie_setup(struct pci_sys_data *sys)
0140 {
0141     struct resource *res;
0142     struct resource realio;
0143     int dev;
0144
0145     /*
0146      * Generic PCIe unit setup.
0147      */
0148     orion_pcie_setup(PCIE_BASE);
0149
0150     /*
0151      * Check whether to apply Orion-1/Orion-NAS PCIe config
0152      * read transaction workaround.
0153      */
0154     dev = orion_pcie_dev_id(PCIE_BASE);
0155     if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
0156         printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
0157                    "read transaction workaround\n");
0158         mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
0159                         ORION_MBUS_PCIE_WA_ATTR,
0160                         ORION5X_PCIE_WA_PHYS_BASE,
0161                         ORION5X_PCIE_WA_SIZE);
0162         pcie_ops.read = pcie_rd_conf_wa;
0163     }
0164
0165     realio.start = sys->busnr * SZ_64K;
0166     realio.end = realio.start + SZ_64K - 1;
0167     pci_remap_iospace(&realio, ORION5X_PCIE_IO_PHYS_BASE);
0168
0169     /*
0170      * Request resources.
0171      */
0172     res = kzalloc(sizeof(struct resource), GFP_KERNEL);
0173     if (!res)
0174         panic("pcie_setup unable to alloc resources");
0175
0176     /*
0177      * IORESOURCE_MEM
0178      */
0179     res->name = "PCIe Memory Space";
0180     res->flags = IORESOURCE_MEM;
0181     res->start = ORION5X_PCIE_MEM_PHYS_BASE;
0182     res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
0183     if (request_resource(&iomem_resource, res))
0184         panic("Request PCIe Memory resource failed\n");
0185     pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
0186
0187     return 1;
0188 }
0189
0190 /*****************************************************************************
0191  * PCI controller
0192  ****************************************************************************/
0193 #define ORION5X_PCI_REG(x)  (ORION5X_PCI_VIRT_BASE + (x))
0194 #define PCI_MODE        ORION5X_PCI_REG(0xd00)
0195 #define PCI_CMD         ORION5X_PCI_REG(0xc00)
0196 #define PCI_P2P_CONF        ORION5X_PCI_REG(0x1d14)
0197 #define PCI_CONF_ADDR       ORION5X_PCI_REG(0xc78)
0198 #define PCI_CONF_DATA       ORION5X_PCI_REG(0xc7c)
0199
0200 /*
0201  * PCI_MODE bits
0202  */
0203 #define PCI_MODE_64BIT          (1 << 2)
0204 #define PCI_MODE_PCIX           ((1 << 4) | (1 << 5))
0205
0206 /*
0207  * PCI_CMD bits
0208  */
0209 #define PCI_CMD_HOST_REORDER        (1 << 29)
0210
0211 /*
0212  * PCI_P2P_CONF bits
0213  */
0214 #define PCI_P2P_BUS_OFFS        16
0215 #define PCI_P2P_BUS_MASK        (0xff << PCI_P2P_BUS_OFFS)
0216 #define PCI_P2P_DEV_OFFS        24
0217 #define PCI_P2P_DEV_MASK        (0x1f << PCI_P2P_DEV_OFFS)
0218
0219 /*
0220  * PCI_CONF_ADDR bits
0221  */
0222 #define PCI_CONF_REG(reg)       ((reg) & 0xfc)
0223 #define PCI_CONF_FUNC(func)     (((func) & 0x3) << 8)
0224 #define PCI_CONF_DEV(dev)       (((dev) & 0x1f) << 11)
0225 #define PCI_CONF_BUS(bus)       (((bus) & 0xff) << 16)
0226 #define PCI_CONF_ADDR_EN        (1 << 31)
0227
0228 /*
0229  * Internal configuration space
0230  */
0231 #define PCI_CONF_FUNC_STAT_CMD      0
0232 #define PCI_CONF_REG_STAT_CMD       4
0233 #define PCIX_STAT           0x64
0234 #define PCIX_STAT_BUS_OFFS      8
0235 #define PCIX_STAT_BUS_MASK      (0xff << PCIX_STAT_BUS_OFFS)
0236
0237 /*
0238  * PCI Address Decode Windows registers
0239  */
0240 #define PCI_BAR_SIZE_DDR_CS(n)  (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
0241                  ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
0242                  ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
0243                  ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : NULL)
0244 #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
0245                  ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
0246                  ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
0247                  ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : NULL)
0248 #define PCI_BAR_ENABLE      ORION5X_PCI_REG(0xc3c)
0249 #define PCI_ADDR_DECODE_CTRL    ORION5X_PCI_REG(0xd3c)
0250
0251 /*
0252  * PCI configuration helpers for BAR settings
0253  */
0254 #define PCI_CONF_FUNC_BAR_CS(n)     ((n) >> 1)
0255 #define PCI_CONF_REG_BAR_LO_CS(n)   (((n) & 1) ? 0x18 : 0x10)
0256 #define PCI_CONF_REG_BAR_HI_CS(n)   (((n) & 1) ? 0x1c : 0x14)
0257
0258 /*
0259  * PCI config cycles are done by programming the PCI_CONF_ADDR register
0260  * and then reading the PCI_CONF_DATA register. Need to make sure these
0261  * transactions are atomic.
0262  */
0263 static DEFINE_SPINLOCK(orion5x_pci_lock);
0264
0265 static int orion5x_pci_cardbus_mode;
0266
0267 static int orion5x_pci_local_bus_nr(void)
0268 {
0269     u32 conf = readl(PCI_P2P_CONF);
0270     return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
0271 }
0272
0273 static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
0274                     u32 where, u32 size, u32 *val)
0275 {
0276     unsigned long flags;
0277     spin_lock_irqsave(&orion5x_pci_lock, flags);
0278
0279     writel(PCI_CONF_BUS(bus) |
0280         PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
0281         PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
0282
0283     *val = readl(PCI_CONF_DATA);
0284
0285     if (size == 1)
0286         *val = (*val >> (8*(where & 0x3))) & 0xff;
0287     else if (size == 2)
0288         *val = (*val >> (8*(where & 0x3))) & 0xffff;
0289
0290     spin_unlock_irqrestore(&orion5x_pci_lock, flags);
0291
0292     return PCIBIOS_SUCCESSFUL;
0293 }
0294
0295 static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
0296                     u32 where, u32 size, u32 val)
0297 {
0298     unsigned long flags;
0299     int ret = PCIBIOS_SUCCESSFUL;
0300
0301     spin_lock_irqsave(&orion5x_pci_lock, flags);
0302
0303     writel(PCI_CONF_BUS(bus) |
0304         PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
0305         PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
0306
0307     if (size == 4) {
0308         __raw_writel(val, PCI_CONF_DATA);
0309     } else if (size == 2) {
0310         __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
0311     } else if (size == 1) {
0312         __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
0313     } else {
0314         ret = PCIBIOS_BAD_REGISTER_NUMBER;
0315     }
0316
0317     spin_unlock_irqrestore(&orion5x_pci_lock, flags);
0318
0319     return ret;
0320 }
0321
0322 static int orion5x_pci_valid_config(int bus, u32 devfn)
0323 {
0324     if (bus == orion5x_pci_local_bus_nr()) {
0325         /*
0326          * Don't go out for local device
0327          */
0328         if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
0329             return 0;
0330
0331         /*
0332          * When the PCI signals are directly connected to a
0333          * Cardbus slot, ignore all but device IDs 0 and 1.
0334          */
0335         if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
0336             return 0;
0337     }
0338
0339     return 1;
0340 }
0341
0342 static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
0343                 int where, int size, u32 *val)
0344 {
0345     if (!orion5x_pci_valid_config(bus->number, devfn)) {
0346         *val = 0xffffffff;
0347         return PCIBIOS_DEVICE_NOT_FOUND;
0348     }
0349
0350     return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
0351                     PCI_FUNC(devfn), where, size, val);
0352 }
0353
0354 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
0355                 int where, int size, u32 val)
0356 {
0357     if (!orion5x_pci_valid_config(bus->number, devfn))
0358         return PCIBIOS_DEVICE_NOT_FOUND;
0359
0360     return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
0361                     PCI_FUNC(devfn), where, size, val);
0362 }
0363
0364 static struct pci_ops pci_ops = {
0365     .read = orion5x_pci_rd_conf,
0366     .write = orion5x_pci_wr_conf,
0367 };
0368
0369 static void __init orion5x_pci_set_bus_nr(int nr)
0370 {
0371     u32 p2p = readl(PCI_P2P_CONF);
0372
0373     if (readl(PCI_MODE) & PCI_MODE_PCIX) {
0374         /*
0375          * PCI-X mode
0376          */
0377         u32 pcix_status, bus, dev;
0378         bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
0379         dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
0380         orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
0381         pcix_status &= ~PCIX_STAT_BUS_MASK;
0382         pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
0383         orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
0384     } else {
0385         /*
0386          * PCI Conventional mode
0387          */
0388         p2p &= ~PCI_P2P_BUS_MASK;
0389         p2p |= (nr << PCI_P2P_BUS_OFFS);
0390         writel(p2p, PCI_P2P_CONF);
0391     }
0392 }
0393
0394 static void __init orion5x_pci_master_slave_enable(void)
0395 {
0396     int bus_nr, func, reg;
0397     u32 val;
0398
0399     bus_nr = orion5x_pci_local_bus_nr();
0400     func = PCI_CONF_FUNC_STAT_CMD;
0401     reg = PCI_CONF_REG_STAT_CMD;
0402     orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
0403     val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
0404     orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
0405 }
0406
0407 static void __init orion5x_setup_pci_wins(void)
0408 {
0409     const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
0410     u32 win_enable;
0411     int bus;
0412     int i;
0413
0414     /*
0415      * First, disable windows.
0416      */
0417     win_enable = 0xffffffff;
0418     writel(win_enable, PCI_BAR_ENABLE);
0419
0420     /*
0421      * Setup windows for DDR banks.
0422      */
0423     bus = orion5x_pci_local_bus_nr();
0424
0425     for (i = 0; i < dram->num_cs; i++) {
0426         const struct mbus_dram_window *cs = dram->cs + i;
0427         u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
0428         u32 reg;
0429         u32 val;
0430
0431         /*
0432          * Write DRAM bank base address register.
0433          */
0434         reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
0435         orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
0436         val = (cs->base & 0xfffff000) | (val & 0xfff);
0437         orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
0438
0439         /*
0440          * Write DRAM bank size register.
0441          */
0442         reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
0443         orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
0444         writel((cs->size - 1) & 0xfffff000,
0445             PCI_BAR_SIZE_DDR_CS(cs->cs_index));
0446         writel(cs->base & 0xfffff000,
0447             PCI_BAR_REMAP_DDR_CS(cs->cs_index));
0448
0449         /*
0450          * Enable decode window for this chip select.
0451          */
0452         win_enable &= ~(1 << cs->cs_index);
0453     }
0454
0455     /*
0456      * Re-enable decode windows.
0457      */
0458     writel(win_enable, PCI_BAR_ENABLE);
0459
0460     /*
0461      * Disable automatic update of address remapping when writing to BARs.
0462      */
0463     orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
0464 }
0465
0466 static int __init pci_setup(struct pci_sys_data *sys)
0467 {
0468     struct resource *res;
0469     struct resource realio;
0470
0471     /*
0472      * Point PCI unit MBUS decode windows to DRAM space.
0473      */
0474     orion5x_setup_pci_wins();
0475
0476     /*
0477      * Master + Slave enable
0478      */
0479     orion5x_pci_master_slave_enable();
0480
0481     /*
0482      * Force ordering
0483      */
0484     orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
0485
0486     realio.start = sys->busnr * SZ_64K;
0487     realio.end = realio.start + SZ_64K - 1;
0488     pci_remap_iospace(&realio, ORION5X_PCI_IO_PHYS_BASE);
0489
0490     /*
0491      * Request resources
0492      */
0493     res = kzalloc(sizeof(struct resource), GFP_KERNEL);
0494     if (!res)
0495         panic("pci_setup unable to alloc resources");
0496
0497     /*
0498      * IORESOURCE_MEM
0499      */
0500     res->name = "PCI Memory Space";
0501     res->flags = IORESOURCE_MEM;
0502     res->start = ORION5X_PCI_MEM_PHYS_BASE;
0503     res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
0504     if (request_resource(&iomem_resource, res))
0505         panic("Request PCI Memory resource failed\n");
0506     pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
0507
0508     return 1;
0509 }
0510
0511
0512 /*****************************************************************************
0513  * General PCIe + PCI
0514  ****************************************************************************/
0515
0516 /*
0517  * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
0518  * is operating as a root complex this needs to be switched to
0519  * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
0520  * the device. Decoding setup is handled by the orion code.
0521  */
0522 static void rc_pci_fixup(struct pci_dev *dev)
0523 {
0524     if (dev->bus->parent == NULL && dev->devfn == 0) {
0525         int i;
0526
0527         dev->class &= 0xff;
0528         dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
0529         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
0530             dev->resource[i].start = 0;
0531             dev->resource[i].end   = 0;
0532             dev->resource[i].flags = 0;
0533         }
0534     }
0535 }
0536 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
0537
0538 static int orion5x_pci_disabled __initdata;
0539
0540 void __init orion5x_pci_disable(void)
0541 {
0542     orion5x_pci_disabled = 1;
0543 }
0544
0545 void __init orion5x_pci_set_cardbus_mode(void)
0546 {
0547     orion5x_pci_cardbus_mode = 1;
0548 }
0549
0550 int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
0551 {
0552     vga_base = ORION5X_PCIE_MEM_PHYS_BASE;
0553
0554     if (nr == 0) {
0555         orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
0556         return pcie_setup(sys);
0557     }
0558
0559     if (nr == 1 && !orion5x_pci_disabled) {
0560         orion5x_pci_set_bus_nr(sys->busnr);
0561         return pci_setup(sys);
0562     }
0563
0564     return 0;
0565 }
0566
0567 int __init orion5x_pci_sys_scan_bus(int nr, struct pci_host_bridge *bridge)
0568 {
0569     struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
0570
0571     list_splice_init(&sys->resources, &bridge->windows);
0572     bridge->dev.parent = NULL;
0573     bridge->sysdata = sys;
0574     bridge->busnr = sys->busnr;
0575
0576     if (nr == 0) {
0577         bridge->ops = &pcie_ops;
0578         return pci_scan_root_bus_bridge(bridge);
0579     }
0580
0581     if (nr == 1 && !orion5x_pci_disabled) {
0582         bridge->ops = &pci_ops;
0583         return pci_scan_root_bus_bridge(bridge);
0584     }
0585
0586     BUG();
0587     return -ENODEV;
0588 }
0589
0590 int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0591 {
0592     int bus = dev->bus->number;
0593
0594     /*
0595      * PCIe endpoint?
0596      */
0597     if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
0598         return IRQ_ORION5X_PCIE0_INT;
0599
0600     return -1;
0601 }