arm/mach-orion5x/bridge-regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Orion CPU Bridge Registers */
0003
0004 #ifndef __ASM_ARCH_BRIDGE_REGS_H
0005 #define __ASM_ARCH_BRIDGE_REGS_H
0006
0007 #include "orion5x.h"
0008
0009 #define CPU_CONF        (ORION5X_BRIDGE_VIRT_BASE + 0x100)
0010
0011 #define CPU_CTRL        (ORION5X_BRIDGE_VIRT_BASE + 0x104)
0012
0013 #define RSTOUTn_MASK        (ORION5X_BRIDGE_VIRT_BASE + 0x108)
0014 #define RSTOUTn_MASK_PHYS   (ORION5X_BRIDGE_PHYS_BASE + 0x108)
0015
0016 #define CPU_SOFT_RESET      (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
0017
0018 #define BRIDGE_CAUSE        (ORION5X_BRIDGE_VIRT_BASE + 0x110)
0019
0020 #define POWER_MNG_CTRL_REG  (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
0021
0022 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
0023
0024 #define MAIN_IRQ_CAUSE      (ORION5X_BRIDGE_VIRT_BASE + 0x200)
0025
0026 #define MAIN_IRQ_MASK       (ORION5X_BRIDGE_VIRT_BASE + 0x204)
0027
0028 #define TIMER_VIRT_BASE     (ORION5X_BRIDGE_VIRT_BASE + 0x300)
0029 #define TIMER_PHYS_BASE     (ORION5X_BRIDGE_PHYS_BASE + 0x300)
0030 #endif