arm/mach-omap2/wd_timer.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * OMAP2+ MPU WD_TIMER-specific code
0004  *
0005  * Copyright (C) 2012 Texas Instruments, Inc.
0006  */
0007
0008 #include <linux/kernel.h>
0009 #include <linux/io.h>
0010 #include <linux/err.h>
0011
0012 #include <linux/platform_data/omap-wd-timer.h>
0013
0014 #include "omap_hwmod.h"
0015 #include "omap_device.h"
0016 #include "wd_timer.h"
0017 #include "common.h"
0018 #include "prm.h"
0019 #include "soc.h"
0020
0021 /*
0022  * In order to avoid any assumptions from bootloader regarding WDT
0023  * settings, WDT module is reset during init. This enables the watchdog
0024  * timer. Hence it is required to disable the watchdog after the WDT reset
0025  * during init. Otherwise the system would reboot as per the default
0026  * watchdog timer registers settings.
0027  */
0028 #define OMAP_WDT_WPS        0x34
0029 #define OMAP_WDT_SPR        0x48
0030
0031 int omap2_wd_timer_disable(struct omap_hwmod *oh)
0032 {
0033     void __iomem *base;
0034
0035     if (!oh) {
0036         pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
0037         return -EINVAL;
0038     }
0039
0040     base = omap_hwmod_get_mpu_rt_va(oh);
0041     if (!base) {
0042         pr_err("%s: Could not get the base address for %s\n",
0043                 oh->name, __func__);
0044         return -EINVAL;
0045     }
0046
0047     /* sequence required to disable watchdog */
0048     writel_relaxed(0xAAAA, base + OMAP_WDT_SPR);
0049     while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
0050         cpu_relax();
0051
0052     writel_relaxed(0x5555, base + OMAP_WDT_SPR);
0053     while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
0054         cpu_relax();
0055
0056     return 0;
0057 }
0058
0059 /**
0060  * omap2_wdtimer_reset - reset and disable the WDTIMER IP block
0061  * @oh: struct omap_hwmod *
0062  *
0063  * After the WDTIMER IP blocks are reset on OMAP2/3, we must also take
0064  * care to execute the special watchdog disable sequence.  This is
0065  * because the watchdog is re-armed upon OCP softreset.  (On OMAP4,
0066  * this behavior was apparently changed and the watchdog is no longer
0067  * re-armed after an OCP soft-reset.)  Returns -ETIMEDOUT if the reset
0068  * did not complete, or 0 upon success.
0069  *
0070  * XXX Most of this code should be moved to the omap_hwmod.c layer
0071  * during a normal merge window.  omap_hwmod_softreset() should be
0072  * renamed to omap_hwmod_set_ocp_softreset(), and omap_hwmod_softreset()
0073  * should call the hwmod _ocp_softreset() code.
0074  */
0075 int omap2_wd_timer_reset(struct omap_hwmod *oh)
0076 {
0077     int c = 0;
0078
0079     /* Write to the SOFTRESET bit */
0080     omap_hwmod_softreset(oh);
0081
0082     /* Poll on RESETDONE bit */
0083     omap_test_timeout((omap_hwmod_read(oh,
0084                        oh->class->sysc->syss_offs)
0085                & SYSS_RESETDONE_MASK),
0086               MAX_MODULE_SOFTRESET_WAIT, c);
0087
0088     if (oh->class->sysc->srst_udelay)
0089         udelay(oh->class->sysc->srst_udelay);
0090
0091     if (c == MAX_MODULE_SOFTRESET_WAIT)
0092         pr_warn("%s: %s: softreset failed (waited %d usec)\n",
0093             __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
0094     else
0095         pr_debug("%s: %s: softreset in %d usec\n", __func__,
0096              oh->name, c);
0097
0098     return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT :
0099         omap2_wd_timer_disable(oh);
0100 }