arm/mach-omap2/vc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * OMAP3/4 Voltage Controller (VC) structure and macro definitions
0004  *
0005  * Copyright (C) 2007, 2010 Texas Instruments, Inc.
0006  * Rajendra Nayak <rnayak@ti.com>
0007  * Lesly A M <x0080970@ti.com>
0008  * Thara Gopinath <thara@ti.com>
0009  *
0010  * Copyright (C) 2008, 2011 Nokia Corporation
0011  * Kalle Jokiniemi
0012  * Paul Walmsley
0013  */
0014 #ifndef __ARCH_ARM_MACH_OMAP2_VC_H
0015 #define __ARCH_ARM_MACH_OMAP2_VC_H
0016
0017 #include <linux/kernel.h>
0018
0019 struct voltagedomain;
0020
0021 /**
0022  * struct omap_vc_common - per-VC register/bitfield data
0023  * @cmd_on_mask: ON bitmask in PRM_VC_CMD_VAL* register
0024  * @valid: VALID bitmask in PRM_VC_BYPASS_VAL register
0025  * @bypass_val_reg: Offset of PRM_VC_BYPASS_VAL reg from PRM start
0026  * @data_shift: DATA field shift in PRM_VC_BYPASS_VAL register
0027  * @slaveaddr_shift: SLAVEADDR field shift in PRM_VC_BYPASS_VAL register
0028  * @regaddr_shift: REGADDR field shift in PRM_VC_BYPASS_VAL register
0029  * @cmd_on_shift: ON field shift in PRM_VC_CMD_VAL_* register
0030  * @cmd_onlp_shift: ONLP field shift in PRM_VC_CMD_VAL_* register
0031  * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
0032  * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
0033  * @i2c_cfg_reg: I2C configuration register offset
0034  * @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register
0035  * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
0036  * @i2c_mcode_mask: MCODE field mask for I2C config register
0037  *
0038  * XXX One of cmd_on_mask and cmd_on_shift are not needed
0039  * XXX VALID should probably be a shift, not a mask
0040  */
0041 struct omap_vc_common {
0042     u32 cmd_on_mask;
0043     u32 valid;
0044     u8 bypass_val_reg;
0045     u8 data_shift;
0046     u8 slaveaddr_shift;
0047     u8 regaddr_shift;
0048     u8 cmd_on_shift;
0049     u8 cmd_onlp_shift;
0050     u8 cmd_ret_shift;
0051     u8 cmd_off_shift;
0052     u8 i2c_cfg_reg;
0053     u8 i2c_cfg_clear_mask;
0054     u8 i2c_cfg_hsen_mask;
0055     u8 i2c_mcode_mask;
0056 };
0057
0058 /* omap_vc_channel.flags values */
0059 #define OMAP_VC_CHANNEL_DEFAULT BIT(0)
0060 #define OMAP_VC_CHANNEL_CFG_MUTANT BIT(1)
0061
0062 /**
0063  * struct omap_vc_channel - VC per-instance data
0064  * @i2c_slave_addr: I2C slave address of PMIC for this VC channel
0065  * @volt_reg_addr: voltage configuration register address
0066  * @cmd_reg_addr: command configuration register address
0067  * @setup_time: setup time (in sys_clk cycles) of regulator for this channel
0068  * @cfg_channel: current value of VC channel configuration register
0069  * @i2c_high_speed: whether or not to use I2C high-speed mode
0070  *
0071  * @common: pointer to VC common data for this platform
0072  * @smps_sa_mask: i2c slave address bitmask in the PRM_VC_SMPS_SA register
0073  * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
0074  * @smps_cmdra_mask: CMDRA* bitmask in the PRM_VC_CMD_RA register
0075  * @cmdval_reg: register for on/ret/off voltage level values for this channel
0076  * @smps_sa_reg: Offset of PRM_VC_SMPS_SA reg from PRM start
0077  * @smps_volra_reg: Offset of PRM_VC_SMPS_VOL_RA reg from PRM start
0078  * @smps_cmdra_reg: Offset of PRM_VC_SMPS_CMD_RA reg from PRM start
0079  * @cfg_channel_reg: VC channel configuration register
0080  * @cfg_channel_sa_shift: bit shift for slave address cfg_channel register
0081  * @flags: VC channel-specific flags (optional)
0082  */
0083 struct omap_vc_channel {
0084     /* channel state */
0085     u16 i2c_slave_addr;
0086     u16 volt_reg_addr;
0087     u16 cmd_reg_addr;
0088     u8 cfg_channel;
0089     bool i2c_high_speed;
0090
0091     /* register access data */
0092     const struct omap_vc_common *common;
0093     u32 smps_sa_mask;
0094     u32 smps_volra_mask;
0095     u32 smps_cmdra_mask;
0096     u8 cmdval_reg;
0097     u8 smps_sa_reg;
0098     u8 smps_volra_reg;
0099     u8 smps_cmdra_reg;
0100     u8 cfg_channel_reg;
0101     u8 cfg_channel_sa_shift;
0102     u8 flags;
0103 };
0104
0105 extern struct omap_vc_channel omap3_vc_mpu;
0106 extern struct omap_vc_channel omap3_vc_core;
0107
0108 extern struct omap_vc_channel omap4_vc_mpu;
0109 extern struct omap_vc_channel omap4_vc_iva;
0110 extern struct omap_vc_channel omap4_vc_core;
0111
0112 extern struct omap_vc_param omap3_mpu_vc_data;
0113 extern struct omap_vc_param omap3_core_vc_data;
0114
0115 extern struct omap_vc_param omap4_mpu_vc_data;
0116 extern struct omap_vc_param omap4_iva_vc_data;
0117 extern struct omap_vc_param omap4_core_vc_data;
0118
0119 void omap3_vc_set_pmic_signaling(int core_next_state);
0120 void omap4_vc_set_pmic_signaling(int core_next_state);
0121
0122 void omap_vc_init_channel(struct voltagedomain *voltdm);
0123 int omap_vc_pre_scale(struct voltagedomain *voltdm,
0124               unsigned long target_volt,
0125               u8 *target_vsel, u8 *current_vsel);
0126 void omap_vc_post_scale(struct voltagedomain *voltdm,
0127             unsigned long target_volt,
0128             u8 target_vsel, u8 current_vsel);
0129 int omap_vc_bypass_scale(struct voltagedomain *voltdm,
0130              unsigned long target_volt);
0131
0132 #endif
0133