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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * OMAP Voltage Controller (VC) interface
0004  *
0005  * Copyright (C) 2011 Texas Instruments, Inc.
0006  */
0007 #include <linux/kernel.h>
0008 #include <linux/delay.h>
0009 #include <linux/init.h>
0010 #include <linux/bug.h>
0011 #include <linux/io.h>
0012 
0013 #include <asm/div64.h>
0014 
0015 #include "iomap.h"
0016 #include "soc.h"
0017 #include "voltage.h"
0018 #include "vc.h"
0019 #include "prm-regbits-34xx.h"
0020 #include "prm-regbits-44xx.h"
0021 #include "prm44xx.h"
0022 #include "pm.h"
0023 #include "scrm44xx.h"
0024 #include "control.h"
0025 
0026 #define OMAP4430_VDD_IVA_I2C_DISABLE        BIT(14)
0027 #define OMAP4430_VDD_MPU_I2C_DISABLE        BIT(13)
0028 #define OMAP4430_VDD_CORE_I2C_DISABLE       BIT(12)
0029 #define OMAP4430_VDD_IVA_PRESENCE       BIT(9)
0030 #define OMAP4430_VDD_MPU_PRESENCE       BIT(8)
0031 #define OMAP4430_AUTO_CTRL_VDD_IVA(x)       ((x) << 4)
0032 #define OMAP4430_AUTO_CTRL_VDD_MPU(x)       ((x) << 2)
0033 #define OMAP4430_AUTO_CTRL_VDD_CORE(x)      ((x) << 0)
0034 #define OMAP4430_AUTO_CTRL_VDD_RET      2
0035 
0036 #define OMAP4430_VDD_I2C_DISABLE_MASK   \
0037     (OMAP4430_VDD_IVA_I2C_DISABLE | \
0038      OMAP4430_VDD_MPU_I2C_DISABLE | \
0039      OMAP4430_VDD_CORE_I2C_DISABLE)
0040 
0041 #define OMAP4_VDD_DEFAULT_VAL   \
0042     (OMAP4430_VDD_I2C_DISABLE_MASK | \
0043      OMAP4430_VDD_IVA_PRESENCE | OMAP4430_VDD_MPU_PRESENCE | \
0044      OMAP4430_AUTO_CTRL_VDD_IVA(OMAP4430_AUTO_CTRL_VDD_RET) | \
0045      OMAP4430_AUTO_CTRL_VDD_MPU(OMAP4430_AUTO_CTRL_VDD_RET) | \
0046      OMAP4430_AUTO_CTRL_VDD_CORE(OMAP4430_AUTO_CTRL_VDD_RET))
0047 
0048 #define OMAP4_VDD_RET_VAL   \
0049     (OMAP4_VDD_DEFAULT_VAL & ~OMAP4430_VDD_I2C_DISABLE_MASK)
0050 
0051 /**
0052  * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
0053  * @sa: bit for slave address
0054  * @rav: bit for voltage configuration register
0055  * @rac: bit for command configuration register
0056  * @racen: enable bit for RAC
0057  * @cmd: bit for command value set selection
0058  *
0059  * Channel configuration bits, common for OMAP3+
0060  * OMAP3 register: PRM_VC_CH_CONF
0061  * OMAP4 register: PRM_VC_CFG_CHANNEL
0062  * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
0063  */
0064 struct omap_vc_channel_cfg {
0065     u8 sa;
0066     u8 rav;
0067     u8 rac;
0068     u8 racen;
0069     u8 cmd;
0070 };
0071 
0072 static struct omap_vc_channel_cfg vc_default_channel_cfg = {
0073     .sa    = BIT(0),
0074     .rav   = BIT(1),
0075     .rac   = BIT(2),
0076     .racen = BIT(3),
0077     .cmd   = BIT(4),
0078 };
0079 
0080 /*
0081  * On OMAP3+, all VC channels have the above default bitfield
0082  * configuration, except the OMAP4 MPU channel.  This appears
0083  * to be a freak accident as every other VC channel has the
0084  * default configuration, thus creating a mutant channel config.
0085  */
0086 static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
0087     .sa    = BIT(0),
0088     .rav   = BIT(2),
0089     .rac   = BIT(3),
0090     .racen = BIT(4),
0091     .cmd   = BIT(1),
0092 };
0093 
0094 static struct omap_vc_channel_cfg *vc_cfg_bits;
0095 
0096 /* Default I2C trace length on pcb, 6.3cm. Used for capacitance calculations. */
0097 static u32 sr_i2c_pcb_length = 63;
0098 #define CFG_CHANNEL_MASK 0x1f
0099 
0100 /**
0101  * omap_vc_config_channel - configure VC channel to PMIC mappings
0102  * @voltdm: pointer to voltagdomain defining the desired VC channel
0103  *
0104  * Configures the VC channel to PMIC mappings for the following
0105  * PMIC settings
0106  * - i2c slave address (SA)
0107  * - voltage configuration address (RAV)
0108  * - command configuration address (RAC) and enable bit (RACEN)
0109  * - command values for ON, ONLP, RET and OFF (CMD)
0110  *
0111  * This function currently only allows flexible configuration of the
0112  * non-default channel.  Starting with OMAP4, there are more than 2
0113  * channels, with one defined as the default (on OMAP4, it's MPU.)
0114  * Only the non-default channel can be configured.
0115  */
0116 static int omap_vc_config_channel(struct voltagedomain *voltdm)
0117 {
0118     struct omap_vc_channel *vc = voltdm->vc;
0119 
0120     /*
0121      * For default channel, the only configurable bit is RACEN.
0122      * All others must stay at zero (see function comment above.)
0123      */
0124     if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
0125         vc->cfg_channel &= vc_cfg_bits->racen;
0126 
0127     voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
0128             vc->cfg_channel << vc->cfg_channel_sa_shift,
0129             vc->cfg_channel_reg);
0130 
0131     return 0;
0132 }
0133 
0134 /* Voltage scale and accessory APIs */
0135 int omap_vc_pre_scale(struct voltagedomain *voltdm,
0136               unsigned long target_volt,
0137               u8 *target_vsel, u8 *current_vsel)
0138 {
0139     struct omap_vc_channel *vc = voltdm->vc;
0140     u32 vc_cmdval;
0141 
0142     /* Check if sufficient pmic info is available for this vdd */
0143     if (!voltdm->pmic) {
0144         pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
0145             __func__, voltdm->name);
0146         return -EINVAL;
0147     }
0148 
0149     if (!voltdm->pmic->uv_to_vsel) {
0150         pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
0151                __func__, voltdm->name);
0152         return -ENODATA;
0153     }
0154 
0155     if (!voltdm->read || !voltdm->write) {
0156         pr_err("%s: No read/write API for accessing vdd_%s regs\n",
0157             __func__, voltdm->name);
0158         return -EINVAL;
0159     }
0160 
0161     *target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
0162     *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
0163 
0164     /* Setting the ON voltage to the new target voltage */
0165     vc_cmdval = voltdm->read(vc->cmdval_reg);
0166     vc_cmdval &= ~vc->common->cmd_on_mask;
0167     vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
0168     voltdm->write(vc_cmdval, vc->cmdval_reg);
0169 
0170     voltdm->vc_param->on = target_volt;
0171 
0172     omap_vp_update_errorgain(voltdm, target_volt);
0173 
0174     return 0;
0175 }
0176 
0177 void omap_vc_post_scale(struct voltagedomain *voltdm,
0178             unsigned long target_volt,
0179             u8 target_vsel, u8 current_vsel)
0180 {
0181     u32 smps_steps = 0, smps_delay = 0;
0182 
0183     smps_steps = abs(target_vsel - current_vsel);
0184     /* SMPS slew rate / step size. 2us added as buffer. */
0185     smps_delay = ((smps_steps * voltdm->pmic->step_size) /
0186             voltdm->pmic->slew_rate) + 2;
0187     udelay(smps_delay);
0188 }
0189 
0190 /* vc_bypass_scale - VC bypass method of voltage scaling */
0191 int omap_vc_bypass_scale(struct voltagedomain *voltdm,
0192              unsigned long target_volt)
0193 {
0194     struct omap_vc_channel *vc = voltdm->vc;
0195     u32 loop_cnt = 0, retries_cnt = 0;
0196     u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
0197     u8 target_vsel, current_vsel;
0198     int ret;
0199 
0200     ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
0201     if (ret)
0202         return ret;
0203 
0204     vc_valid = vc->common->valid;
0205     vc_bypass_val_reg = vc->common->bypass_val_reg;
0206     vc_bypass_value = (target_vsel << vc->common->data_shift) |
0207         (vc->volt_reg_addr << vc->common->regaddr_shift) |
0208         (vc->i2c_slave_addr << vc->common->slaveaddr_shift);
0209 
0210     voltdm->write(vc_bypass_value, vc_bypass_val_reg);
0211     voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
0212 
0213     vc_bypass_value = voltdm->read(vc_bypass_val_reg);
0214     /*
0215      * Loop till the bypass command is acknowledged from the SMPS.
0216      * NOTE: This is legacy code. The loop count and retry count needs
0217      * to be revisited.
0218      */
0219     while (!(vc_bypass_value & vc_valid)) {
0220         loop_cnt++;
0221 
0222         if (retries_cnt > 10) {
0223             pr_warn("%s: Retry count exceeded\n", __func__);
0224             return -ETIMEDOUT;
0225         }
0226 
0227         if (loop_cnt > 50) {
0228             retries_cnt++;
0229             loop_cnt = 0;
0230             udelay(10);
0231         }
0232         vc_bypass_value = voltdm->read(vc_bypass_val_reg);
0233     }
0234 
0235     omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
0236     return 0;
0237 }
0238 
0239 /* Convert microsecond value to number of 32kHz clock cycles */
0240 static inline u32 omap_usec_to_32k(u32 usec)
0241 {
0242     return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL);
0243 }
0244 
0245 struct omap3_vc_timings {
0246     u32 voltsetup1;
0247     u32 voltsetup2;
0248 };
0249 
0250 struct omap3_vc {
0251     struct voltagedomain *vd;
0252     u32 voltctrl;
0253     u32 voltsetup1;
0254     u32 voltsetup2;
0255     struct omap3_vc_timings timings[2];
0256 };
0257 static struct omap3_vc vc;
0258 
0259 void omap3_vc_set_pmic_signaling(int core_next_state)
0260 {
0261     struct voltagedomain *vd = vc.vd;
0262     struct omap3_vc_timings *c = vc.timings;
0263     u32 voltctrl, voltsetup1, voltsetup2;
0264 
0265     voltctrl = vc.voltctrl;
0266     voltsetup1 = vc.voltsetup1;
0267     voltsetup2 = vc.voltsetup2;
0268 
0269     switch (core_next_state) {
0270     case PWRDM_POWER_OFF:
0271         voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET |
0272                   OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
0273         voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_OFF;
0274         if (voltctrl & OMAP3430_PRM_VOLTCTRL_SEL_OFF)
0275             voltsetup2 = c->voltsetup2;
0276         else
0277             voltsetup1 = c->voltsetup1;
0278         break;
0279     case PWRDM_POWER_RET:
0280     default:
0281         c++;
0282         voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF |
0283                   OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
0284         voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_RET;
0285         voltsetup1 = c->voltsetup1;
0286         break;
0287     }
0288 
0289     if (voltctrl != vc.voltctrl) {
0290         vd->write(voltctrl, OMAP3_PRM_VOLTCTRL_OFFSET);
0291         vc.voltctrl = voltctrl;
0292     }
0293     if (voltsetup1 != vc.voltsetup1) {
0294         vd->write(c->voltsetup1,
0295               OMAP3_PRM_VOLTSETUP1_OFFSET);
0296         vc.voltsetup1 = voltsetup1;
0297     }
0298     if (voltsetup2 != vc.voltsetup2) {
0299         vd->write(c->voltsetup2,
0300               OMAP3_PRM_VOLTSETUP2_OFFSET);
0301         vc.voltsetup2 = voltsetup2;
0302     }
0303 }
0304 
0305 void omap4_vc_set_pmic_signaling(int core_next_state)
0306 {
0307     struct voltagedomain *vd = vc.vd;
0308     u32 val;
0309 
0310     if (!vd)
0311         return;
0312 
0313     switch (core_next_state) {
0314     case PWRDM_POWER_RET:
0315         val = OMAP4_VDD_RET_VAL;
0316         break;
0317     default:
0318         val = OMAP4_VDD_DEFAULT_VAL;
0319         break;
0320     }
0321 
0322     vd->write(val, OMAP4_PRM_VOLTCTRL_OFFSET);
0323 }
0324 
0325 /*
0326  * Configure signal polarity for sys_clkreq and sys_off_mode pins
0327  * as the default values are wrong and can cause the system to hang
0328  * if any twl4030 scripts are loaded.
0329  */
0330 static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm)
0331 {
0332     u32 val;
0333 
0334     if (vc.vd)
0335         return;
0336 
0337     vc.vd = voltdm;
0338 
0339     val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET);
0340     if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) ||
0341         (val & OMAP3430_PRM_POLCTRL_OFFMODE_POL)) {
0342         val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL;
0343         val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL;
0344         pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n",
0345              val);
0346         voltdm->write(val, OMAP3_PRM_POLCTRL_OFFSET);
0347     }
0348 
0349     /*
0350      * By default let's use I2C4 signaling for retention idle
0351      * and sys_off_mode pin signaling for off idle. This way we
0352      * have sys_clk_req pin go down for retention and both
0353      * sys_clk_req and sys_off_mode pins will go down for off
0354      * idle. And we can also scale voltages to zero for off-idle.
0355      * Note that no actual voltage scaling during off-idle will
0356      * happen unless the board specific twl4030 PMIC scripts are
0357      * loaded. See also omap_vc_i2c_init for comments regarding
0358      * erratum i531.
0359      */
0360     val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
0361     if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) {
0362         val |= OMAP3430_PRM_VOLTCTRL_SEL_OFF;
0363         pr_debug("PM: setting voltctrl sys_off_mode signaling to 0x%x\n",
0364              val);
0365         voltdm->write(val, OMAP3_PRM_VOLTCTRL_OFFSET);
0366     }
0367     vc.voltctrl = val;
0368 
0369     omap3_vc_set_pmic_signaling(PWRDM_POWER_ON);
0370 }
0371 
0372 static void omap3_init_voltsetup1(struct voltagedomain *voltdm,
0373                   struct omap3_vc_timings *c, u32 idle)
0374 {
0375     unsigned long val;
0376 
0377     val = (voltdm->vc_param->on - idle) / voltdm->pmic->slew_rate;
0378     val *= voltdm->sys_clk.rate / 8 / 1000000 + 1;
0379     val <<= __ffs(voltdm->vfsm->voltsetup_mask);
0380     c->voltsetup1 &= ~voltdm->vfsm->voltsetup_mask;
0381     c->voltsetup1 |= val;
0382 }
0383 
0384 /**
0385  * omap3_set_i2c_timings - sets i2c sleep timings for a channel
0386  * @voltdm: channel to configure
0387  * @off_mode: select whether retention or off mode values used
0388  *
0389  * Calculates and sets up voltage controller to use I2C based
0390  * voltage scaling for sleep modes. This can be used for either off mode
0391  * or retention. Off mode has additionally an option to use sys_off_mode
0392  * pad, which uses a global signal to program the whole power IC to
0393  * off-mode.
0394  *
0395  * Note that pmic is not controlling the voltage scaling during
0396  * retention signaled over I2C4, so we can keep voltsetup2 as 0.
0397  * And the oscillator is not shut off over I2C4, so no need to
0398  * set clksetup.
0399  */
0400 static void omap3_set_i2c_timings(struct voltagedomain *voltdm)
0401 {
0402     struct omap3_vc_timings *c = vc.timings;
0403 
0404     /* Configure PRWDM_POWER_OFF over I2C4 */
0405     omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->off);
0406     c++;
0407     /* Configure PRWDM_POWER_RET over I2C4 */
0408     omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->ret);
0409 }
0410 
0411 /**
0412  * omap3_set_off_timings - sets off-mode timings for a channel
0413  * @voltdm: channel to configure
0414  *
0415  * Calculates and sets up off-mode timings for a channel. Off-mode
0416  * can use either I2C based voltage scaling, or alternatively
0417  * sys_off_mode pad can be used to send a global command to power IC.n,
0418  * sys_off_mode has the additional benefit that voltages can be
0419  * scaled to zero volt level with TWL4030 / TWL5030, I2C can only
0420  * scale to 600mV.
0421  *
0422  * Note that omap is not controlling the voltage scaling during
0423  * off idle signaled by sys_off_mode, so we can keep voltsetup1
0424  * as 0.
0425  */
0426 static void omap3_set_off_timings(struct voltagedomain *voltdm)
0427 {
0428     struct omap3_vc_timings *c = vc.timings;
0429     u32 tstart, tshut, clksetup, voltoffset;
0430 
0431     if (c->voltsetup2)
0432         return;
0433 
0434     omap_pm_get_oscillator(&tstart, &tshut);
0435     if (tstart == ULONG_MAX) {
0436         pr_debug("PM: oscillator start-up time not initialized, using 10ms\n");
0437         clksetup = omap_usec_to_32k(10000);
0438     } else {
0439         clksetup = omap_usec_to_32k(tstart);
0440     }
0441 
0442     /*
0443      * For twl4030 errata 27, we need to allow minimum ~488.32 us wait to
0444      * switch from HFCLKIN to internal oscillator. That means timings
0445      * have voltoffset fixed to 0xa in rounded up 32 KiHz cycles. And
0446      * that means we can calculate the value based on the oscillator
0447      * start-up time since voltoffset2 = clksetup - voltoffset.
0448      */
0449     voltoffset = omap_usec_to_32k(488);
0450     c->voltsetup2 = clksetup - voltoffset;
0451     voltdm->write(clksetup, OMAP3_PRM_CLKSETUP_OFFSET);
0452     voltdm->write(voltoffset, OMAP3_PRM_VOLTOFFSET_OFFSET);
0453 }
0454 
0455 static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
0456 {
0457     omap3_vc_init_pmic_signaling(voltdm);
0458     omap3_set_off_timings(voltdm);
0459     omap3_set_i2c_timings(voltdm);
0460 }
0461 
0462 /**
0463  * omap4_calc_volt_ramp - calculates voltage ramping delays on omap4
0464  * @voltdm: channel to calculate values for
0465  * @voltage_diff: voltage difference in microvolts
0466  *
0467  * Calculates voltage ramp prescaler + counter values for a voltage
0468  * difference on omap4. Returns a field value suitable for writing to
0469  * VOLTSETUP register for a channel in following format:
0470  * bits[8:9] prescaler ... bits[0:5] counter. See OMAP4 TRM for reference.
0471  */
0472 static u32 omap4_calc_volt_ramp(struct voltagedomain *voltdm, u32 voltage_diff)
0473 {
0474     u32 prescaler;
0475     u32 cycles;
0476     u32 time;
0477 
0478     time = voltage_diff / voltdm->pmic->slew_rate;
0479 
0480     cycles = voltdm->sys_clk.rate / 1000 * time / 1000;
0481 
0482     cycles /= 64;
0483     prescaler = 0;
0484 
0485     /* shift to next prescaler until no overflow */
0486 
0487     /* scale for div 256 = 64 * 4 */
0488     if (cycles > 63) {
0489         cycles /= 4;
0490         prescaler++;
0491     }
0492 
0493     /* scale for div 512 = 256 * 2 */
0494     if (cycles > 63) {
0495         cycles /= 2;
0496         prescaler++;
0497     }
0498 
0499     /* scale for div 2048 = 512 * 4 */
0500     if (cycles > 63) {
0501         cycles /= 4;
0502         prescaler++;
0503     }
0504 
0505     /* check for overflow => invalid ramp time */
0506     if (cycles > 63) {
0507         pr_warn("%s: invalid setuptime for vdd_%s\n", __func__,
0508             voltdm->name);
0509         return 0;
0510     }
0511 
0512     cycles++;
0513 
0514     return (prescaler << OMAP4430_RAMP_UP_PRESCAL_SHIFT) |
0515         (cycles << OMAP4430_RAMP_UP_COUNT_SHIFT);
0516 }
0517 
0518 /**
0519  * omap4_usec_to_val_scrm - convert microsecond value to SCRM module bitfield
0520  * @usec: microseconds
0521  * @shift: number of bits to shift left
0522  * @mask: bitfield mask
0523  *
0524  * Converts microsecond value to OMAP4 SCRM bitfield. Bitfield is
0525  * shifted to requested position, and checked agains the mask value.
0526  * If larger, forced to the max value of the field (i.e. the mask itself.)
0527  * Returns the SCRM bitfield value.
0528  */
0529 static u32 omap4_usec_to_val_scrm(u32 usec, int shift, u32 mask)
0530 {
0531     u32 val;
0532 
0533     val = omap_usec_to_32k(usec) << shift;
0534 
0535     /* Check for overflow, if yes, force to max value */
0536     if (val > mask)
0537         val = mask;
0538 
0539     return val;
0540 }
0541 
0542 /**
0543  * omap4_set_timings - set voltage ramp timings for a channel
0544  * @voltdm: channel to configure
0545  * @off_mode: whether off-mode values are used
0546  *
0547  * Calculates and sets the voltage ramp up / down values for a channel.
0548  */
0549 static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
0550 {
0551     u32 val;
0552     u32 ramp;
0553     int offset;
0554     u32 tstart, tshut;
0555 
0556     if (off_mode) {
0557         ramp = omap4_calc_volt_ramp(voltdm,
0558             voltdm->vc_param->on - voltdm->vc_param->off);
0559         offset = voltdm->vfsm->voltsetup_off_reg;
0560     } else {
0561         ramp = omap4_calc_volt_ramp(voltdm,
0562             voltdm->vc_param->on - voltdm->vc_param->ret);
0563         offset = voltdm->vfsm->voltsetup_reg;
0564     }
0565 
0566     if (!ramp)
0567         return;
0568 
0569     val = voltdm->read(offset);
0570 
0571     val |= ramp << OMAP4430_RAMP_DOWN_COUNT_SHIFT;
0572 
0573     val |= ramp << OMAP4430_RAMP_UP_COUNT_SHIFT;
0574 
0575     voltdm->write(val, offset);
0576 
0577     omap_pm_get_oscillator(&tstart, &tshut);
0578 
0579     val = omap4_usec_to_val_scrm(tstart, OMAP4_SETUPTIME_SHIFT,
0580         OMAP4_SETUPTIME_MASK);
0581     val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT,
0582         OMAP4_DOWNTIME_MASK);
0583 
0584     writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME);
0585 }
0586 
0587 static void __init omap4_vc_init_pmic_signaling(struct voltagedomain *voltdm)
0588 {
0589     if (vc.vd)
0590         return;
0591 
0592     vc.vd = voltdm;
0593     voltdm->write(OMAP4_VDD_DEFAULT_VAL, OMAP4_PRM_VOLTCTRL_OFFSET);
0594 }
0595 
0596 /* OMAP4 specific voltage init functions */
0597 static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
0598 {
0599     omap4_vc_init_pmic_signaling(voltdm);
0600     omap4_set_timings(voltdm, true);
0601     omap4_set_timings(voltdm, false);
0602 }
0603 
0604 struct i2c_init_data {
0605     u8 loadbits;
0606     u8 load;
0607     u8 hsscll_38_4;
0608     u8 hsscll_26;
0609     u8 hsscll_19_2;
0610     u8 hsscll_16_8;
0611     u8 hsscll_12;
0612 };
0613 
0614 static const struct i2c_init_data omap4_i2c_timing_data[] __initconst = {
0615     {
0616         .load = 50,
0617         .loadbits = 0x3,
0618         .hsscll_38_4 = 13,
0619         .hsscll_26 = 11,
0620         .hsscll_19_2 = 9,
0621         .hsscll_16_8 = 9,
0622         .hsscll_12 = 8,
0623     },
0624     {
0625         .load = 25,
0626         .loadbits = 0x2,
0627         .hsscll_38_4 = 13,
0628         .hsscll_26 = 11,
0629         .hsscll_19_2 = 9,
0630         .hsscll_16_8 = 9,
0631         .hsscll_12 = 8,
0632     },
0633     {
0634         .load = 12,
0635         .loadbits = 0x1,
0636         .hsscll_38_4 = 11,
0637         .hsscll_26 = 10,
0638         .hsscll_19_2 = 9,
0639         .hsscll_16_8 = 9,
0640         .hsscll_12 = 8,
0641     },
0642     {
0643         .load = 0,
0644         .loadbits = 0x0,
0645         .hsscll_38_4 = 12,
0646         .hsscll_26 = 10,
0647         .hsscll_19_2 = 9,
0648         .hsscll_16_8 = 8,
0649         .hsscll_12 = 8,
0650     },
0651 };
0652 
0653 /**
0654  * omap4_vc_i2c_timing_init - sets up board I2C timing parameters
0655  * @voltdm: voltagedomain pointer to get data from
0656  *
0657  * Use PMIC + board supplied settings for calculating the total I2C
0658  * channel capacitance and set the timing parameters based on this.
0659  * Pre-calculated values are provided in data tables, as it is not
0660  * too straightforward to calculate these runtime.
0661  */
0662 static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
0663 {
0664     u32 capacitance;
0665     u32 val;
0666     u16 hsscll;
0667     const struct i2c_init_data *i2c_data;
0668 
0669     if (!voltdm->pmic->i2c_high_speed) {
0670         pr_info("%s: using bootloader low-speed timings\n", __func__);
0671         return;
0672     }
0673 
0674     /* PCB trace capacitance, 0.125pF / mm => mm / 8 */
0675     capacitance = DIV_ROUND_UP(sr_i2c_pcb_length, 8);
0676 
0677     /* OMAP pad capacitance */
0678     capacitance += 4;
0679 
0680     /* PMIC pad capacitance */
0681     capacitance += voltdm->pmic->i2c_pad_load;
0682 
0683     /* Search for capacitance match in the table */
0684     i2c_data = omap4_i2c_timing_data;
0685 
0686     while (i2c_data->load > capacitance)
0687         i2c_data++;
0688 
0689     /* Select proper values based on sysclk frequency */
0690     switch (voltdm->sys_clk.rate) {
0691     case 38400000:
0692         hsscll = i2c_data->hsscll_38_4;
0693         break;
0694     case 26000000:
0695         hsscll = i2c_data->hsscll_26;
0696         break;
0697     case 19200000:
0698         hsscll = i2c_data->hsscll_19_2;
0699         break;
0700     case 16800000:
0701         hsscll = i2c_data->hsscll_16_8;
0702         break;
0703     case 12000000:
0704         hsscll = i2c_data->hsscll_12;
0705         break;
0706     default:
0707         pr_warn("%s: unsupported sysclk rate: %d!\n", __func__,
0708             voltdm->sys_clk.rate);
0709         return;
0710     }
0711 
0712     /* Loadbits define pull setup for the I2C channels */
0713     val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29;
0714 
0715     /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */
0716     writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
0717                 OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2));
0718 
0719     /* HSSCLH can always be zero */
0720     val = hsscll << OMAP4430_HSSCLL_SHIFT;
0721     val |= (0x28 << OMAP4430_SCLL_SHIFT | 0x2c << OMAP4430_SCLH_SHIFT);
0722 
0723     /* Write setup times to I2C config register */
0724     voltdm->write(val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
0725 }
0726 
0727 
0728 
0729 /**
0730  * omap_vc_i2c_init - initialize I2C interface to PMIC
0731  * @voltdm: voltage domain containing VC data
0732  *
0733  * Use PMIC supplied settings for I2C high-speed mode and
0734  * master code (if set) and program the VC I2C configuration
0735  * register.
0736  *
0737  * The VC I2C configuration is common to all VC channels,
0738  * so this function only configures I2C for the first VC
0739  * channel registers.  All other VC channels will use the
0740  * same configuration.
0741  */
0742 static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
0743 {
0744     struct omap_vc_channel *vc = voltdm->vc;
0745     static bool initialized;
0746     static bool i2c_high_speed;
0747     u8 mcode;
0748 
0749     if (initialized) {
0750         if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
0751             pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).\n",
0752                 __func__, voltdm->name, i2c_high_speed);
0753         return;
0754     }
0755 
0756     /*
0757      * Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around
0758      * erratum i531 "Extra Power Consumed When Repeated Start Operation
0759      * Mode Is Enabled on I2C Interface Dedicated for Smart Reflex (I2C4)".
0760      * Otherwise I2C4 eventually leads into about 23mW extra power being
0761      * consumed even during off idle using VMODE.
0762      */
0763     i2c_high_speed = voltdm->pmic->i2c_high_speed;
0764     if (i2c_high_speed)
0765         voltdm->rmw(vc->common->i2c_cfg_clear_mask,
0766                 vc->common->i2c_cfg_hsen_mask,
0767                 vc->common->i2c_cfg_reg);
0768 
0769     mcode = voltdm->pmic->i2c_mcode;
0770     if (mcode)
0771         voltdm->rmw(vc->common->i2c_mcode_mask,
0772                 mcode << __ffs(vc->common->i2c_mcode_mask),
0773                 vc->common->i2c_cfg_reg);
0774 
0775     if (cpu_is_omap44xx())
0776         omap4_vc_i2c_timing_init(voltdm);
0777 
0778     initialized = true;
0779 }
0780 
0781 /**
0782  * omap_vc_calc_vsel - calculate vsel value for a channel
0783  * @voltdm: channel to calculate value for
0784  * @uvolt: microvolt value to convert to vsel
0785  *
0786  * Converts a microvolt value to vsel value for the used PMIC.
0787  * This checks whether the microvolt value is out of bounds, and
0788  * adjusts the value accordingly. If unsupported value detected,
0789  * warning is thrown.
0790  */
0791 static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt)
0792 {
0793     if (voltdm->pmic->vddmin > uvolt)
0794         uvolt = voltdm->pmic->vddmin;
0795     if (voltdm->pmic->vddmax < uvolt) {
0796         WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n",
0797             __func__, uvolt, voltdm->pmic->vddmax);
0798         /* Lets try maximum value anyway */
0799         uvolt = voltdm->pmic->vddmax;
0800     }
0801 
0802     return voltdm->pmic->uv_to_vsel(uvolt);
0803 }
0804 
0805 #ifdef CONFIG_PM
0806 /**
0807  * omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB
0808  * @mm: length of the PCB trace in millimetres
0809  *
0810  * Sets the PCB trace length for the I2C channel. By default uses 63mm.
0811  * This is needed for properly calculating the capacitance value for
0812  * the PCB trace, and for setting the SR I2C channel timing parameters.
0813  */
0814 void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm)
0815 {
0816     sr_i2c_pcb_length = mm;
0817 }
0818 #endif
0819 
0820 void __init omap_vc_init_channel(struct voltagedomain *voltdm)
0821 {
0822     struct omap_vc_channel *vc = voltdm->vc;
0823     u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
0824     u32 val;
0825 
0826     if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
0827         pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
0828         return;
0829     }
0830 
0831     if (!voltdm->read || !voltdm->write) {
0832         pr_err("%s: No read/write API for accessing vdd_%s regs\n",
0833             __func__, voltdm->name);
0834         return;
0835     }
0836 
0837     vc->cfg_channel = 0;
0838     if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
0839         vc_cfg_bits = &vc_mutant_channel_cfg;
0840     else
0841         vc_cfg_bits = &vc_default_channel_cfg;
0842 
0843     /* get PMIC/board specific settings */
0844     vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
0845     vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
0846     vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
0847 
0848     /* Configure the i2c slave address for this VC */
0849     voltdm->rmw(vc->smps_sa_mask,
0850             vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
0851             vc->smps_sa_reg);
0852     vc->cfg_channel |= vc_cfg_bits->sa;
0853 
0854     /*
0855      * Configure the PMIC register addresses.
0856      */
0857     voltdm->rmw(vc->smps_volra_mask,
0858             vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
0859             vc->smps_volra_reg);
0860     vc->cfg_channel |= vc_cfg_bits->rav;
0861 
0862     if (vc->cmd_reg_addr) {
0863         voltdm->rmw(vc->smps_cmdra_mask,
0864                 vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
0865                 vc->smps_cmdra_reg);
0866         vc->cfg_channel |= vc_cfg_bits->rac;
0867     }
0868 
0869     if (vc->cmd_reg_addr == vc->volt_reg_addr)
0870         vc->cfg_channel |= vc_cfg_bits->racen;
0871 
0872     /* Set up the on, inactive, retention and off voltage */
0873     on_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->on);
0874     onlp_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->onlp);
0875     ret_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->ret);
0876     off_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->off);
0877 
0878     val = ((on_vsel << vc->common->cmd_on_shift) |
0879            (onlp_vsel << vc->common->cmd_onlp_shift) |
0880            (ret_vsel << vc->common->cmd_ret_shift) |
0881            (off_vsel << vc->common->cmd_off_shift));
0882     voltdm->write(val, vc->cmdval_reg);
0883     vc->cfg_channel |= vc_cfg_bits->cmd;
0884 
0885     /* Channel configuration */
0886     omap_vc_config_channel(voltdm);
0887 
0888     omap_vc_i2c_init(voltdm);
0889 
0890     if (cpu_is_omap34xx())
0891         omap3_vc_init_channel(voltdm);
0892     else if (cpu_is_omap44xx())
0893         omap4_vc_init_channel(voltdm);
0894 }
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