arm/mach-omap2/sdrc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 #ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
0003 #define __ARCH_ARM_MACH_OMAP2_SDRC_H
0004
0005 /*
0006  * OMAP2/3 SDRC/SMS macros and prototypes
0007  *
0008  * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
0009  * Copyright (C) 2007-2008 Nokia Corporation
0010  *
0011  * Paul Walmsley
0012  * Tony Lindgren
0013  * Richard Woodruff
0014  */
0015 #undef DEBUG
0016
0017 #ifndef __ASSEMBLER__
0018
0019 #include <linux/io.h>
0020
0021 extern void __iomem *omap2_sdrc_base;
0022 extern void __iomem *omap2_sms_base;
0023
0024 #define OMAP_SDRC_REGADDR(reg)          (omap2_sdrc_base + (reg))
0025 #define OMAP_SMS_REGADDR(reg)           (omap2_sms_base + (reg))
0026
0027 /* SDRC global register get/set */
0028
0029 static inline void sdrc_write_reg(u32 val, u16 reg)
0030 {
0031     writel_relaxed(val, OMAP_SDRC_REGADDR(reg));
0032 }
0033
0034 static inline u32 sdrc_read_reg(u16 reg)
0035 {
0036     return readl_relaxed(OMAP_SDRC_REGADDR(reg));
0037 }
0038
0039 /* SMS global register get/set */
0040
0041 static inline void sms_write_reg(u32 val, u16 reg)
0042 {
0043     writel_relaxed(val, OMAP_SMS_REGADDR(reg));
0044 }
0045
0046 static inline u32 sms_read_reg(u16 reg)
0047 {
0048     return readl_relaxed(OMAP_SMS_REGADDR(reg));
0049 }
0050
0051 extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms);
0052
0053
0054 /**
0055  * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
0056  * @rate: SDRC clock rate (in Hz)
0057  * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
0058  * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
0059  * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
0060  * @mr: Value to program to SDRC_MR for this rate
0061  *
0062  * This structure holds a pre-computed set of register values for the
0063  * SDRC for a given SDRC clock rate and SDRAM chip.  These are
0064  * intended to be pre-computed and specified in an array in the board-*.c
0065  * files.  The structure is keyed off the 'rate' field.
0066  */
0067 struct omap_sdrc_params {
0068     unsigned long rate;
0069     u32 actim_ctrla;
0070     u32 actim_ctrlb;
0071     u32 rfr_ctrl;
0072     u32 mr;
0073 };
0074
0075 #ifdef CONFIG_SOC_HAS_OMAP2_SDRC
0076 void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
0077                 struct omap_sdrc_params *sdrc_cs1);
0078 #else
0079 static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
0080                       struct omap_sdrc_params *sdrc_cs1) {};
0081 #endif
0082
0083 int omap2_sdrc_get_params(unsigned long r,
0084               struct omap_sdrc_params **sdrc_cs0,
0085               struct omap_sdrc_params **sdrc_cs1);
0086 void omap2_sms_save_context(void);
0087 void omap2_sms_restore_context(void);
0088
0089 struct memory_timings {
0090     u32 m_type;     /* ddr = 1, sdr = 0 */
0091     u32 dll_mode;       /* use lock mode = 1, unlock mode = 0 */
0092     u32 slow_dll_ctrl;  /* unlock mode, dll value for slow speed */
0093     u32 fast_dll_ctrl;  /* unlock mode, dll value for fast speed */
0094     u32 base_cs;        /* base chip select to use for calculations */
0095 };
0096
0097 extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
0098 struct omap_sdrc_params *rx51_get_sdram_timings(void);
0099
0100 u32 omap2xxx_sdrc_dll_is_unlocked(void);
0101 u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
0102
0103
0104 #else
0105 #define OMAP242X_SDRC_REGADDR(reg)                  \
0106             OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
0107 #define OMAP243X_SDRC_REGADDR(reg)                  \
0108             OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
0109 #define OMAP34XX_SDRC_REGADDR(reg)                  \
0110             OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
0111
0112 #endif  /* __ASSEMBLER__ */
0113
0114 /* Minimum frequency that the SDRC DLL can lock at */
0115 #define MIN_SDRC_DLL_LOCK_FREQ      83000000
0116
0117 /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
0118 #define SDRC_MPURATE_SCALE      8
0119
0120 /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
0121 #define SDRC_MPURATE_BASE_SHIFT     9
0122
0123 /*
0124  * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
0125  * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
0126  */
0127 #define SDRC_MPURATE_LOOPS      96
0128
0129 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
0130
0131 #define SDRC_SYSCONFIG      0x010
0132 #define SDRC_CS_CFG     0x040
0133 #define SDRC_SHARING        0x044
0134 #define SDRC_ERR_TYPE       0x04C
0135 #define SDRC_DLLA_CTRL      0x060
0136 #define SDRC_DLLA_STATUS    0x064
0137 #define SDRC_DLLB_CTRL      0x068
0138 #define SDRC_DLLB_STATUS    0x06C
0139 #define SDRC_POWER      0x070
0140 #define SDRC_MCFG_0     0x080
0141 #define SDRC_MR_0       0x084
0142 #define SDRC_EMR2_0     0x08c
0143 #define SDRC_ACTIM_CTRL_A_0 0x09c
0144 #define SDRC_ACTIM_CTRL_B_0 0x0a0
0145 #define SDRC_RFR_CTRL_0     0x0a4
0146 #define SDRC_MANUAL_0       0x0a8
0147 #define SDRC_MCFG_1     0x0B0
0148 #define SDRC_MR_1       0x0B4
0149 #define SDRC_EMR2_1     0x0BC
0150 #define SDRC_ACTIM_CTRL_A_1 0x0C4
0151 #define SDRC_ACTIM_CTRL_B_1 0x0C8
0152 #define SDRC_RFR_CTRL_1     0x0D4
0153 #define SDRC_MANUAL_1       0x0D8
0154
0155 #define SDRC_POWER_AUTOCOUNT_SHIFT  8
0156 #define SDRC_POWER_AUTOCOUNT_MASK   (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
0157 #define SDRC_POWER_CLKCTRL_SHIFT    4
0158 #define SDRC_POWER_CLKCTRL_MASK     (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
0159 #define SDRC_SELF_REFRESH_ON_AUTOCOUNT  (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
0160
0161 /*
0162  * These values represent the number of memory clock cycles between
0163  * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
0164  * rows per device, and include a subtraction of a 50 cycle window in the
0165  * event that the autorefresh command is delayed due to other SDRC activity.
0166  * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
0167  * counter reaches 0.
0168  *
0169  * These represent optimal values for common parts, it won't work for all.
0170  * As long as you scale down, most parameters are still work, they just
0171  * become sub-optimal. The RFR value goes in the opposite direction. If you
0172  * don't adjust it down as your clock period increases the refresh interval
0173  * will not be met. Setting all parameters for complete worst case may work,
0174  * but may cut memory performance by 2x. Due to errata the DLLs need to be
0175  * unlocked and their value needs run time calibration. A dynamic call is
0176  * need for that as no single right value exists across production samples.
0177  *
0178  * Only the FULL speed values are given. Current code is such that rate
0179  * changes must be made at DPLLoutx2. The actual value adjustment for low
0180  * frequency operation will be handled by omap_set_performance()
0181  *
0182  * By having the boot loader boot up in the fastest L4 speed available likely
0183  * will result in something which you can switch between.
0184  */
0185 #define SDRC_RFR_CTRL_165MHz    (0x00044c00 | 1)
0186 #define SDRC_RFR_CTRL_133MHz    (0x0003de00 | 1)
0187 #define SDRC_RFR_CTRL_100MHz    (0x0002da01 | 1)
0188 #define SDRC_RFR_CTRL_110MHz    (0x0002da01 | 1) /* Need to calc */
0189 #define SDRC_RFR_CTRL_BYPASS    (0x00005000 | 1) /* Need to calc */
0190
0191
0192 /*
0193  * SMS register access
0194  */
0195
0196 #define OMAP242X_SMS_REGADDR(reg)                   \
0197         (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
0198 #define OMAP243X_SMS_REGADDR(reg)                   \
0199         (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
0200 #define OMAP343X_SMS_REGADDR(reg)                   \
0201         (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
0202
0203 /* SMS register offsets - read/write with sms_{read,write}_reg() */
0204
0205 #define SMS_SYSCONFIG           0x010
0206 /* REVISIT: fill in other SMS registers here */
0207
0208
0209
0210 #endif