arm/mach-omap2/sdrc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * SMS/SDRC (SDRAM controller) common code for OMAP2/3
0004  *
0005  * Copyright (C) 2005, 2008 Texas Instruments Inc.
0006  * Copyright (C) 2005, 2008 Nokia Corporation
0007  *
0008  * Tony Lindgren <tony@atomide.com>
0009  * Paul Walmsley
0010  * Richard Woodruff <r-woodruff2@ti.com>
0011  */
0012 #undef DEBUG
0013
0014 #include <linux/module.h>
0015 #include <linux/kernel.h>
0016 #include <linux/device.h>
0017 #include <linux/list.h>
0018 #include <linux/errno.h>
0019 #include <linux/delay.h>
0020 #include <linux/clk.h>
0021 #include <linux/io.h>
0022
0023 #include "common.h"
0024 #include "clock.h"
0025 #include "sdrc.h"
0026
0027 static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
0028
0029 void __iomem *omap2_sdrc_base;
0030 void __iomem *omap2_sms_base;
0031
0032 struct omap2_sms_regs {
0033     u32 sms_sysconfig;
0034 };
0035
0036 static struct omap2_sms_regs sms_context;
0037
0038 /* SDRC_POWER register bits */
0039 #define SDRC_POWER_EXTCLKDIS_SHIFT      3
0040 #define SDRC_POWER_PWDENA_SHIFT         2
0041 #define SDRC_POWER_PAGEPOLICY_SHIFT     0
0042
0043 /**
0044  * omap2_sms_save_context - Save SMS registers
0045  *
0046  * Save SMS registers that need to be restored after off mode.
0047  */
0048 void omap2_sms_save_context(void)
0049 {
0050     sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
0051 }
0052
0053 /**
0054  * omap2_sms_restore_context - Restore SMS registers
0055  *
0056  * Restore SMS registers that need to be Restored after off mode.
0057  */
0058 void omap2_sms_restore_context(void)
0059 {
0060     sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
0061 }
0062
0063 /**
0064  * omap2_sdrc_get_params - return SDRC register values for a given clock rate
0065  * @r: SDRC clock rate (in Hz)
0066  * @sdrc_cs0: chip select 0 ram timings **
0067  * @sdrc_cs1: chip select 1 ram timings **
0068  *
0069  * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
0070  *  SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
0071  *  structs,for a given SDRC clock rate 'r'.
0072  * These parameters control various timing delays in the SDRAM controller
0073  *  that are expressed in terms of the number of SDRC clock cycles to
0074  *  wait; hence the clock rate dependency.
0075  *
0076  * Supports 2 different timing parameters for both chip selects.
0077  *
0078  * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
0079  * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
0080  *  as sdrc_init_params_cs_0.
0081  *
0082  * Fills in the struct omap_sdrc_params * for each chip select.
0083  * Returns 0 upon success or -1 upon failure.
0084  */
0085 int omap2_sdrc_get_params(unsigned long r,
0086               struct omap_sdrc_params **sdrc_cs0,
0087               struct omap_sdrc_params **sdrc_cs1)
0088 {
0089     struct omap_sdrc_params *sp0, *sp1;
0090
0091     if (!sdrc_init_params_cs0)
0092         return -1;
0093
0094     sp0 = sdrc_init_params_cs0;
0095     sp1 = sdrc_init_params_cs1;
0096
0097     while (sp0->rate && sp0->rate != r) {
0098         sp0++;
0099         if (sdrc_init_params_cs1)
0100             sp1++;
0101     }
0102
0103     if (!sp0->rate)
0104         return -1;
0105
0106     *sdrc_cs0 = sp0;
0107     *sdrc_cs1 = sp1;
0108     return 0;
0109 }
0110
0111
0112 void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms)
0113 {
0114     omap2_sdrc_base = sdrc;
0115     omap2_sms_base = sms;
0116 }
0117
0118 /**
0119  * omap2_sdrc_init - initialize SMS, SDRC devices on boot
0120  * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
0121  *  Support for 2 chip selects timings
0122  *
0123  * Turn on smart idle modes for SDRAM scheduler and controller.
0124  * Program a known-good configuration for the SDRC to deal with buggy
0125  * bootloaders.
0126  */
0127 void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
0128                 struct omap_sdrc_params *sdrc_cs1)
0129 {
0130     u32 l;
0131
0132     l = sms_read_reg(SMS_SYSCONFIG);
0133     l &= ~(0x3 << 3);
0134     l |= (0x2 << 3);
0135     sms_write_reg(l, SMS_SYSCONFIG);
0136
0137     l = sdrc_read_reg(SDRC_SYSCONFIG);
0138     l &= ~(0x3 << 3);
0139     l |= (0x2 << 3);
0140     sdrc_write_reg(l, SDRC_SYSCONFIG);
0141
0142     sdrc_init_params_cs0 = sdrc_cs0;
0143     sdrc_init_params_cs1 = sdrc_cs1;
0144
0145     /* XXX Enable SRFRONIDLEREQ here also? */
0146     /*
0147      * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
0148      * can cause random memory corruption
0149      */
0150     l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
0151         (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
0152     sdrc_write_reg(l, SDRC_POWER);
0153     omap2_sms_save_context();
0154 }