arm/mach-omap2/prm7xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * DRA7xx PRM instance offset macros
0004  *
0005  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
0006  *
0007  * Generated by code originally written by:
0008  * Paul Walmsley (paul@pwsan.com)
0009  * Rajendra Nayak (rnayak@ti.com)
0010  * Benoit Cousson (b-cousson@ti.com)
0011  *
0012  * This file is automatically generated from the OMAP hardware databases.
0013  * We respectfully ask that any modifications to this file be coordinated
0014  * with the public linux-omap@vger.kernel.org mailing list and the
0015  * authors above to ensure that the autogeneration scripts are kept
0016  * up-to-date with the file contents.
0017  */
0018
0019 #ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
0020 #define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
0021
0022 #include "prcm-common.h"
0023 #include "prm44xx_54xx.h"
0024 #include "prm.h"
0025
0026 #define DRA7XX_PRM_BASE     0x4ae06000
0027
0028 #define DRA7XX_PRM_REGADDR(inst, reg)               \
0029     OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg))
0030
0031
0032 /* PRM instances */
0033 #define DRA7XX_PRM_OCP_SOCKET_INST  0x0000
0034 #define DRA7XX_PRM_CKGEN_INST       0x0100
0035 #define DRA7XX_PRM_MPU_INST     0x0300
0036 #define DRA7XX_PRM_DSP1_INST        0x0400
0037 #define DRA7XX_PRM_IPU_INST     0x0500
0038 #define DRA7XX_PRM_COREAON_INST     0x0628
0039 #define DRA7XX_PRM_CORE_INST        0x0700
0040 #define DRA7XX_PRM_IVA_INST     0x0f00
0041 #define DRA7XX_PRM_CAM_INST     0x1000
0042 #define DRA7XX_PRM_DSS_INST     0x1100
0043 #define DRA7XX_PRM_GPU_INST     0x1200
0044 #define DRA7XX_PRM_L3INIT_INST      0x1300
0045 #define DRA7XX_PRM_L4PER_INST       0x1400
0046 #define DRA7XX_PRM_CUSTEFUSE_INST   0x1600
0047 #define DRA7XX_PRM_WKUPAON_INST     0x1724
0048 #define DRA7XX_PRM_WKUPAON_CM_INST  0x1800
0049 #define DRA7XX_PRM_EMU_INST     0x1900
0050 #define DRA7XX_PRM_EMU_CM_INST      0x1a00
0051 #define DRA7XX_PRM_DSP2_INST        0x1b00
0052 #define DRA7XX_PRM_EVE1_INST        0x1b40
0053 #define DRA7XX_PRM_EVE2_INST        0x1b80
0054 #define DRA7XX_PRM_EVE3_INST        0x1bc0
0055 #define DRA7XX_PRM_EVE4_INST        0x1c00
0056 #define DRA7XX_PRM_RTC_INST     0x1c60
0057 #define DRA7XX_PRM_VPE_INST     0x1c80
0058 #define DRA7XX_PRM_DEVICE_INST      0x1d00
0059
0060 /* PRM clockdomain register offsets (from instance start) */
0061 #define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS    0x0000
0062 #define DRA7XX_PRM_EMU_CM_EMU_CDOFFS        0x0000
0063
0064 /* PRM.CKGEN_PRM register offsets */
0065 #define DRA7XX_CM_CLKSEL_SYS                    DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010)
0066
0067 #endif