arm/mach-omap2/prm44xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * OMAP44xx PRM instance offset macros
0004  *
0005  * Copyright (C) 2009-2011 Texas Instruments, Inc.
0006  * Copyright (C) 2009-2010 Nokia Corporation
0007  *
0008  * Paul Walmsley (paul@pwsan.com)
0009  * Rajendra Nayak (rnayak@ti.com)
0010  * Benoit Cousson (b-cousson@ti.com)
0011  *
0012  * This file is automatically generated from the OMAP hardware databases.
0013  * We respectfully ask that any modifications to this file be coordinated
0014  * with the public linux-omap@vger.kernel.org mailing list and the
0015  * authors above to ensure that the autogeneration scripts are kept
0016  * up-to-date with the file contents.
0017  *
0018  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
0019  *     or "OMAP4430".
0020  */
0021
0022 #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
0023 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
0024
0025 #include "prm44xx_54xx.h"
0026 #include "prm.h"
0027
0028 #define OMAP4430_PRM_BASE       0x4a306000
0029
0030 #define OMAP44XX_PRM_REGADDR(inst, reg)             \
0031     OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
0032
0033
0034 /* PRM instances */
0035 #define OMAP4430_PRM_OCP_SOCKET_INST    0x0000
0036 #define OMAP4430_PRM_CKGEN_INST     0x0100
0037 #define OMAP4430_PRM_MPU_INST       0x0300
0038 #define OMAP4430_PRM_TESLA_INST     0x0400
0039 #define OMAP4430_PRM_ABE_INST       0x0500
0040 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
0041 #define OMAP4430_PRM_CORE_INST      0x0700
0042 #define OMAP4430_PRM_IVAHD_INST     0x0f00
0043 #define OMAP4430_PRM_CAM_INST       0x1000
0044 #define OMAP4430_PRM_DSS_INST       0x1100
0045 #define OMAP4430_PRM_GFX_INST       0x1200
0046 #define OMAP4430_PRM_L3INIT_INST    0x1300
0047 #define OMAP4430_PRM_L4PER_INST     0x1400
0048 #define OMAP4430_PRM_CEFUSE_INST    0x1600
0049 #define OMAP4430_PRM_WKUP_INST      0x1700
0050 #define OMAP4430_PRM_WKUP_CM_INST   0x1800
0051 #define OMAP4430_PRM_EMU_INST       0x1900
0052 #define OMAP4430_PRM_EMU_CM_INST    0x1a00
0053 #define OMAP4430_PRM_DEVICE_INST    0x1b00
0054
0055 /* PRM clockdomain register offsets (from instance start) */
0056 #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS    0x0000
0057 #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS      0x0000
0058
0059 /* OMAP4 specific register offsets */
0060 #define OMAP4_RM_RSTST                  0x0004
0061 #define OMAP4_PM_PWSTCTRL               0x0000
0062 #define OMAP4_PM_PWSTST                 0x0004
0063
0064 /* PRM.OCP_SOCKET_PRM register offsets */
0065 #define OMAP4_REVISION_PRM_OFFSET           0x0000
0066 #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET          0x0010
0067 #define OMAP4430_PRM_IRQSTATUS_MPU          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010)
0068 #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET        0x0014
0069 #define OMAP4_PRM_IRQENABLE_MPU_OFFSET          0x0018
0070 #define OMAP4430_PRM_IRQENABLE_MPU          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018)
0071
0072 /* PRM.MPU_PRM register offsets */
0073 #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET         0x0024
0074
0075 /* PRM.DEVICE_PRM register offsets */
0076 #define OMAP4_PRM_RSTCTRL_OFFSET            0x0000
0077 #define OMAP4_PRM_VOLTCTRL_OFFSET           0x0010
0078 #define OMAP4_PRM_IO_PMCTRL_OFFSET          0x0020
0079 #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET     0x0028
0080 #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET      0x002c
0081 #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET      0x0030
0082 #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET   0x0034
0083 #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET    0x0038
0084 #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET    0x003c
0085 #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET         0x0040
0086 #define OMAP4_PRM_VP_CORE_STATUS_OFFSET         0x0044
0087 #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET       0x0048
0088 #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET        0x004c
0089 #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET       0x0050
0090 #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET       0x0054
0091 #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET          0x0058
0092 #define OMAP4_PRM_VP_MPU_STATUS_OFFSET          0x005c
0093 #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET        0x0060
0094 #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET         0x0064
0095 #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET        0x0068
0096 #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET        0x006c
0097 #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET          0x0070
0098 #define OMAP4_PRM_VP_IVA_STATUS_OFFSET          0x0074
0099 #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET        0x0078
0100 #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET         0x007c
0101 #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET        0x0080
0102 #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET        0x0084
0103 #define OMAP4_PRM_VC_SMPS_SA_OFFSET         0x0088
0104 #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET     0x008c
0105 #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET     0x0090
0106 #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET      0x0094
0107 #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET       0x0098
0108 #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET       0x009c
0109 #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET          0x00a0
0110 #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET         0x00a4
0111 #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET        0x00a8
0112 #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET         0x00ac
0113
0114 #endif