arm/mach-omap2/prm3xxx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * OMAP3xxx Power/Reset Management (PRM) register definitions
0004  *
0005  * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
0006  * Copyright (C) 2008-2010 Nokia Corporation
0007  * Paul Walmsley
0008  *
0009  * The PRM hardware modules on the OMAP2/3 are quite similar to each
0010  * other.  The PRM on OMAP4 has a new register layout, and is handled
0011  * in a separate file.
0012  */
0013 #ifndef __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
0014 #define __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
0015
0016 #include "prcm-common.h"
0017 #include "prm.h"
0018 #include "prm2xxx_3xxx.h"
0019
0020 #define OMAP34XX_PRM_REGADDR(module, reg)               \
0021         OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
0022
0023
0024 /*
0025  * OMAP3-specific global PRM registers
0026  * Use {read,write}l_relaxed() with these registers.
0027  *
0028  * With a few exceptions, these are the register names beginning with
0029  * PRM_* on 34xx.  (The exceptions are the IRQSTATUS and IRQENABLE
0030  * bits.)
0031  */
0032
0033 #define OMAP3_PRM_REVISION_OFFSET   0x0004
0034 #define OMAP3430_PRM_REVISION       OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
0035 #define OMAP3_PRM_SYSCONFIG_OFFSET  0x0014
0036 #define OMAP3430_PRM_SYSCONFIG      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
0037
0038 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET  0x0018
0039 #define OMAP3430_PRM_IRQSTATUS_MPU  OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
0040 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET  0x001c
0041 #define OMAP3430_PRM_IRQENABLE_MPU  OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
0042
0043
0044 #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
0045 #define OMAP3430_PRM_VC_SMPS_SA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
0046 #define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
0047 #define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
0048 #define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
0049 #define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
0050 #define OMAP3_PRM_VC_CMD_VAL_0_OFFSET   0x002c
0051 #define OMAP3430_PRM_VC_CMD_VAL_0   OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
0052 #define OMAP3_PRM_VC_CMD_VAL_1_OFFSET   0x0030
0053 #define OMAP3430_PRM_VC_CMD_VAL_1   OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
0054 #define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
0055 #define OMAP3430_PRM_VC_CH_CONF     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
0056 #define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
0057 #define OMAP3430_PRM_VC_I2C_CFG     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
0058 #define OMAP3_PRM_VC_BYPASS_VAL_OFFSET  0x003c
0059 #define OMAP3430_PRM_VC_BYPASS_VAL  OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
0060 #define OMAP3_PRM_RSTCTRL_OFFSET    0x0050
0061 #define OMAP3430_PRM_RSTCTRL        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
0062 #define OMAP3_PRM_RSTTIME_OFFSET    0x0054
0063 #define OMAP3430_PRM_RSTTIME        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
0064 #define OMAP3_PRM_RSTST_OFFSET  0x0058
0065 #define OMAP3430_PRM_RSTST      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
0066 #define OMAP3_PRM_VOLTCTRL_OFFSET   0x0060
0067 #define OMAP3430_PRM_VOLTCTRL       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
0068 #define OMAP3_PRM_SRAM_PCHARGE_OFFSET   0x0064
0069 #define OMAP3430_PRM_SRAM_PCHARGE   OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
0070 #define OMAP3_PRM_CLKSRC_CTRL_OFFSET    0x0070
0071 #define OMAP3430_PRM_CLKSRC_CTRL    OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
0072 #define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
0073 #define OMAP3430_PRM_VOLTSETUP1     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
0074 #define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
0075 #define OMAP3430_PRM_VOLTOFFSET     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
0076 #define OMAP3_PRM_CLKSETUP_OFFSET   0x0098
0077 #define OMAP3430_PRM_CLKSETUP       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
0078 #define OMAP3_PRM_POLCTRL_OFFSET    0x009c
0079 #define OMAP3430_PRM_POLCTRL        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
0080 #define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
0081 #define OMAP3430_PRM_VOLTSETUP2     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
0082 #define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
0083 #define OMAP3430_PRM_VP1_CONFIG     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
0084 #define OMAP3_PRM_VP1_VSTEPMIN_OFFSET   0x00b4
0085 #define OMAP3430_PRM_VP1_VSTEPMIN   OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
0086 #define OMAP3_PRM_VP1_VSTEPMAX_OFFSET   0x00b8
0087 #define OMAP3430_PRM_VP1_VSTEPMAX   OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
0088 #define OMAP3_PRM_VP1_VLIMITTO_OFFSET   0x00bc
0089 #define OMAP3430_PRM_VP1_VLIMITTO   OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
0090 #define OMAP3_PRM_VP1_VOLTAGE_OFFSET    0x00c0
0091 #define OMAP3430_PRM_VP1_VOLTAGE    OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
0092 #define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
0093 #define OMAP3430_PRM_VP1_STATUS     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
0094 #define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
0095 #define OMAP3430_PRM_VP2_CONFIG     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
0096 #define OMAP3_PRM_VP2_VSTEPMIN_OFFSET   0x00d4
0097 #define OMAP3430_PRM_VP2_VSTEPMIN   OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
0098 #define OMAP3_PRM_VP2_VSTEPMAX_OFFSET   0x00d8
0099 #define OMAP3430_PRM_VP2_VSTEPMAX   OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
0100 #define OMAP3_PRM_VP2_VLIMITTO_OFFSET   0x00dc
0101 #define OMAP3430_PRM_VP2_VLIMITTO   OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
0102 #define OMAP3_PRM_VP2_VOLTAGE_OFFSET    0x00e0
0103 #define OMAP3430_PRM_VP2_VOLTAGE    OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
0104 #define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
0105 #define OMAP3430_PRM_VP2_STATUS     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
0106
0107 #define OMAP3_PRM_CLKSEL_OFFSET 0x0040
0108 #define OMAP3430_PRM_CLKSEL     OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
0109 #define OMAP3_PRM_CLKOUT_CTRL_OFFSET    0x0070
0110 #define OMAP3430_PRM_CLKOUT_CTRL    OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
0111
0112 /* OMAP3 specific register offsets */
0113 #define OMAP3430ES2_PM_WKEN3                0x00f0
0114 #define OMAP3430ES2_PM_WKST3                0x00b8
0115
0116 #define OMAP3430_PM_MPUGRPSEL               0x00a4
0117 #define OMAP3430_PM_MPUGRPSEL1              OMAP3430_PM_MPUGRPSEL
0118 #define OMAP3430ES2_PM_MPUGRPSEL3           0x00f8
0119
0120 #define OMAP3430_PM_IVAGRPSEL               0x00a8
0121 #define OMAP3430_PM_IVAGRPSEL1              OMAP3430_PM_IVAGRPSEL
0122 #define OMAP3430ES2_PM_IVAGRPSEL3           0x00f4
0123
0124 #define OMAP3430_PM_PREPWSTST               0x00e8
0125
0126 #define OMAP3430_PRM_IRQSTATUS_IVA2         0x00f8
0127 #define OMAP3430_PRM_IRQENABLE_IVA2         0x00fc
0128
0129
0130 #ifndef __ASSEMBLER__
0131
0132 /*
0133  * OMAP3 access functions for voltage controller (VC) and
0134  * voltage proccessor (VP) in the PRM.
0135  */
0136 extern u32 omap3_prm_vcvp_read(u8 offset);
0137 extern void omap3_prm_vcvp_write(u32 val, u8 offset);
0138 extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
0139
0140 int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data);
0141 void omap3xxx_prm_iva_idle(void);
0142 void omap3_prm_reset_modem(void);
0143 int omap3xxx_prm_clear_global_cold_reset(void);
0144 void omap3_prm_save_scratchpad_contents(u32 *ptr);
0145 void omap3_prm_init_pm(bool has_uart4, bool has_iva);
0146
0147 #endif /* __ASSEMBLER */
0148
0149
0150 #endif