arm/mach-omap2/prm2xxx_3xxx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions
0004  *
0005  * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
0006  * Copyright (C) 2008-2010 Nokia Corporation
0007  * Paul Walmsley
0008  *
0009  * The PRM hardware modules on the OMAP2/3 are quite similar to each
0010  * other.  The PRM on OMAP4 has a new register layout, and is handled
0011  * in a separate file.
0012  */
0013 #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
0014 #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
0015
0016 #include "prcm-common.h"
0017 #include "prm.h"
0018
0019 /*
0020  * Module specific PRM register offsets from PRM_BASE + domain offset
0021  *
0022  * Use prm_{read,write}_mod_reg() with these registers.
0023  *
0024  * With a few exceptions, these are the register names beginning with
0025  * {PM,RM}_* on both OMAP2/3 SoC families..  (The exceptions are the
0026  * IRQSTATUS and IRQENABLE bits.)
0027  */
0028
0029 /* Register offsets appearing on both OMAP2 and OMAP3 */
0030
0031 #define OMAP2_RM_RSTCTRL                0x0050
0032 #define OMAP2_RM_RSTTIME                0x0054
0033 #define OMAP2_RM_RSTST                  0x0058
0034 #define OMAP2_PM_PWSTCTRL               0x00e0
0035 #define OMAP2_PM_PWSTST                 0x00e4
0036
0037 #define PM_WKEN                     0x00a0
0038 #define PM_WKEN1                    PM_WKEN
0039 #define PM_WKST                     0x00b0
0040 #define PM_WKST1                    PM_WKST
0041 #define PM_WKDEP                    0x00c8
0042 #define PM_EVGENCTRL                    0x00d4
0043 #define PM_EVGENONTIM                   0x00d8
0044 #define PM_EVGENOFFTIM                  0x00dc
0045
0046
0047 #ifndef __ASSEMBLER__
0048
0049 #include <linux/io.h>
0050 #include "powerdomain.h"
0051
0052 /* Power/reset management domain register get/set */
0053 static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
0054 {
0055     return readl_relaxed(prm_base.va + module + idx);
0056 }
0057
0058 static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
0059 {
0060     writel_relaxed(val, prm_base.va + module + idx);
0061 }
0062
0063 /* Read-modify-write a register in a PRM module. Caller must lock */
0064 static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
0065                          s16 idx)
0066 {
0067     u32 v;
0068
0069     v = omap2_prm_read_mod_reg(module, idx);
0070     v &= ~mask;
0071     v |= bits;
0072     omap2_prm_write_mod_reg(v, module, idx);
0073
0074     return v;
0075 }
0076
0077 /* Read a PRM register, AND it, and shift the result down to bit 0 */
0078 static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
0079 {
0080     u32 v;
0081
0082     v = omap2_prm_read_mod_reg(domain, idx);
0083     v &= mask;
0084     v >>= __ffs(mask);
0085
0086     return v;
0087 }
0088
0089 static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
0090 {
0091     return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
0092 }
0093
0094 static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
0095 {
0096     return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
0097 }
0098
0099 /* These omap2_ PRM functions apply to both OMAP2 and 3 */
0100 int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
0101 int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod,
0102                    u16 offset);
0103 int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
0104                  s16 prm_mod, u16 reset_offset,
0105                  u16 st_offset);
0106
0107 extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
0108 extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
0109 extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm);
0110 extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
0111                     u8 pwrst);
0112 extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
0113                      u8 pwrst);
0114 extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
0115 extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
0116 extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
0117 extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm);
0118
0119 extern int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
0120                  struct clockdomain *clkdm2);
0121 extern int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
0122                  struct clockdomain *clkdm2);
0123 extern int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
0124                   struct clockdomain *clkdm2);
0125 extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
0126
0127 #endif /* __ASSEMBLER */
0128
0129 /*
0130  * Bits common to specific registers
0131  *
0132  * The 3430 register and bit names are generally used,
0133  * since they tend to make more sense
0134  */
0135
0136 /* PM_EVGENONTIM_MPU */
0137 /* Named PM_EVEGENONTIM_MPU on the 24XX */
0138 #define OMAP_ONTIMEVAL_SHIFT                0
0139 #define OMAP_ONTIMEVAL_MASK             (0xffffffff << 0)
0140
0141 /* PM_EVGENOFFTIM_MPU */
0142 /* Named PM_EVEGENOFFTIM_MPU on the 24XX */
0143 #define OMAP_OFFTIMEVAL_SHIFT               0
0144 #define OMAP_OFFTIMEVAL_MASK                (0xffffffff << 0)
0145
0146 /* PRM_CLKSETUP and PRCM_VOLTSETUP */
0147 /* Named PRCM_CLKSSETUP on the 24XX */
0148 #define OMAP_SETUP_TIME_SHIFT               0
0149 #define OMAP_SETUP_TIME_MASK                (0xffff << 0)
0150
0151 /* PRM_CLKSRC_CTRL */
0152 /* Named PRCM_CLKSRC_CTRL on the 24XX */
0153 #define OMAP_SYSCLKDIV_SHIFT                6
0154 #define OMAP_SYSCLKDIV_MASK             (0x3 << 6)
0155 #define OMAP_SYSCLKDIV_WIDTH                2
0156 #define OMAP_AUTOEXTCLKMODE_SHIFT           3
0157 #define OMAP_AUTOEXTCLKMODE_MASK            (0x3 << 3)
0158 #define OMAP_SYSCLKSEL_SHIFT                0
0159 #define OMAP_SYSCLKSEL_MASK             (0x3 << 0)
0160
0161 /* PM_EVGENCTRL_MPU */
0162 #define OMAP_OFFLOADMODE_SHIFT              3
0163 #define OMAP_OFFLOADMODE_MASK               (0x3 << 3)
0164 #define OMAP_ONLOADMODE_SHIFT               1
0165 #define OMAP_ONLOADMODE_MASK                (0x3 << 1)
0166 #define OMAP_ENABLE_MASK                (1 << 0)
0167
0168 /* PRM_RSTTIME */
0169 /* Named RM_RSTTIME_WKUP on the 24xx */
0170 #define OMAP_RSTTIME2_SHIFT             8
0171 #define OMAP_RSTTIME2_MASK              (0x1f << 8)
0172 #define OMAP_RSTTIME1_SHIFT             0
0173 #define OMAP_RSTTIME1_MASK              (0xff << 0)
0174
0175 /* PRM_RSTCTRL */
0176 /* Named RM_RSTCTRL_WKUP on the 24xx */
0177 /* 2420 calls RST_DPLL3 'RST_DPLL' */
0178 #define OMAP_RST_DPLL3_MASK             (1 << 2)
0179 #define OMAP_RST_GS_MASK                (1 << 1)
0180
0181
0182 /*
0183  * Bits common to module-shared registers
0184  *
0185  * Not all registers of a particular type support all of these bits -
0186  * check TRM if you are unsure
0187  */
0188
0189 /*
0190  * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
0191  *   called 'COREWKUP_RST'
0192  *
0193  * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
0194  *   RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
0195  */
0196 #define OMAP_COREDOMAINWKUP_RST_MASK            (1 << 3)
0197
0198 /*
0199  * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
0200  *
0201  * 2430: RM_RSTST_MDM
0202  *
0203  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
0204  */
0205 #define OMAP_DOMAINWKUP_RST_MASK            (1 << 2)
0206
0207 /*
0208  * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
0209  *   On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
0210  *
0211  * 2430: RM_RSTST_MDM
0212  *
0213  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
0214  */
0215 #define OMAP_GLOBALWARM_RST_SHIFT           1
0216 #define OMAP_GLOBALWARM_RST_MASK            (1 << 1)
0217 #define OMAP_GLOBALCOLD_RST_SHIFT           0
0218 #define OMAP_GLOBALCOLD_RST_MASK            (1 << 0)
0219
0220 /*
0221  * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
0222  *   2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
0223  *
0224  * 2430: PM_WKDEP_MDM
0225  *
0226  * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
0227  *   PM_WKDEP_PER
0228  */
0229 #define OMAP_EN_WKUP_SHIFT              4
0230 #define OMAP_EN_WKUP_MASK               (1 << 4)
0231
0232 /*
0233  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
0234  *   PM_PWSTCTRL_DSP
0235  *
0236  * 2430: PM_PWSTCTRL_MDM
0237  *
0238  * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
0239  *   PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
0240  *   PM_PWSTCTRL_NEON
0241  */
0242 #define OMAP_LOGICRETSTATE_MASK             (1 << 2)
0243
0244
0245 #endif