arm/mach-omap2/prm2xxx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * OMAP2xxx Power/Reset Management (PRM) register definitions
0004  *
0005  * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
0006  * Copyright (C) 2008-2010 Nokia Corporation
0007  * Paul Walmsley
0008  *
0009  * The PRM hardware modules on the OMAP2/3 are quite similar to each
0010  * other.  The PRM on OMAP4 has a new register layout, and is handled
0011  * in a separate file.
0012  */
0013 #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
0014 #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
0015
0016 #include "prcm-common.h"
0017 #include "prm.h"
0018 #include "prm2xxx_3xxx.h"
0019
0020 #define OMAP2420_PRM_REGADDR(module, reg)               \
0021         OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
0022 #define OMAP2430_PRM_REGADDR(module, reg)               \
0023         OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
0024
0025 /*
0026  * OMAP2-specific global PRM registers
0027  * Use {read,write}l_relaxed() with these registers.
0028  *
0029  * With a few exceptions, these are the register names beginning with
0030  * PRCM_* on 24xx.  (The exceptions are the IRQSTATUS and IRQENABLE
0031  * bits.)
0032  *
0033  */
0034
0035 #define OMAP2_PRCM_REVISION_OFFSET  0x0000
0036 #define OMAP2420_PRCM_REVISION      OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
0037 #define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
0038 #define OMAP2420_PRCM_SYSCONFIG     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
0039
0040 #define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
0041 #define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
0042 #define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
0043 #define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
0044
0045 #define OMAP2_PRCM_VOLTCTRL_OFFSET  0x0050
0046 #define OMAP2420_PRCM_VOLTCTRL      OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
0047 #define OMAP2_PRCM_VOLTST_OFFSET    0x0054
0048 #define OMAP2420_PRCM_VOLTST        OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
0049 #define OMAP2_PRCM_CLKSRC_CTRL_OFFSET   0x0060
0050 #define OMAP2420_PRCM_CLKSRC_CTRL   OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
0051 #define OMAP2_PRCM_CLKOUT_CTRL_OFFSET   0x0070
0052 #define OMAP2420_PRCM_CLKOUT_CTRL   OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
0053 #define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET  0x0078
0054 #define OMAP2420_PRCM_CLKEMUL_CTRL  OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
0055 #define OMAP2_PRCM_CLKCFG_CTRL_OFFSET   0x0080
0056 #define OMAP2420_PRCM_CLKCFG_CTRL   OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
0057 #define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
0058 #define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
0059 #define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
0060 #define OMAP2420_PRCM_VOLTSETUP     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
0061 #define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
0062 #define OMAP2420_PRCM_CLKSSETUP     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
0063 #define OMAP2_PRCM_POLCTRL_OFFSET   0x0098
0064 #define OMAP2420_PRCM_POLCTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
0065
0066 #define OMAP2430_PRCM_REVISION      OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
0067 #define OMAP2430_PRCM_SYSCONFIG     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
0068
0069 #define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
0070 #define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
0071
0072 #define OMAP2430_PRCM_VOLTCTRL      OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
0073 #define OMAP2430_PRCM_VOLTST        OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
0074 #define OMAP2430_PRCM_CLKSRC_CTRL   OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
0075 #define OMAP2430_PRCM_CLKOUT_CTRL   OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
0076 #define OMAP2430_PRCM_CLKEMUL_CTRL  OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
0077 #define OMAP2430_PRCM_CLKCFG_CTRL   OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
0078 #define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
0079 #define OMAP2430_PRCM_VOLTSETUP     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
0080 #define OMAP2430_PRCM_CLKSSETUP     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
0081 #define OMAP2430_PRCM_POLCTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
0082
0083 /*
0084  * Module specific PRM register offsets from PRM_BASE + domain offset
0085  *
0086  * Use prm_{read,write}_mod_reg() with these registers.
0087  *
0088  * With a few exceptions, these are the register names beginning with
0089  * {PM,RM}_* on both OMAP2/3 SoC families..  (The exceptions are the
0090  * IRQSTATUS and IRQENABLE bits.)
0091  */
0092
0093 /* Register offsets appearing on both OMAP2 and OMAP3 */
0094
0095 #define OMAP2_RM_RSTCTRL                0x0050
0096 #define OMAP2_RM_RSTTIME                0x0054
0097 #define OMAP2_RM_RSTST                  0x0058
0098 #define OMAP2_PM_PWSTCTRL               0x00e0
0099 #define OMAP2_PM_PWSTST                 0x00e4
0100
0101 #define PM_WKEN                     0x00a0
0102 #define PM_WKEN1                    PM_WKEN
0103 #define PM_WKST                     0x00b0
0104 #define PM_WKST1                    PM_WKST
0105 #define PM_WKDEP                    0x00c8
0106 #define PM_EVGENCTRL                    0x00d4
0107 #define PM_EVGENONTIM                   0x00d8
0108 #define PM_EVGENOFFTIM                  0x00dc
0109
0110 /* OMAP2xxx specific register offsets */
0111 #define OMAP24XX_PM_WKEN2               0x00a4
0112 #define OMAP24XX_PM_WKST2               0x00b4
0113
0114 #define OMAP24XX_PRCM_IRQSTATUS_DSP         0x00f0  /* IVA mod */
0115 #define OMAP24XX_PRCM_IRQENABLE_DSP         0x00f4  /* IVA mod */
0116 #define OMAP24XX_PRCM_IRQSTATUS_IVA         0x00f8
0117 #define OMAP24XX_PRCM_IRQENABLE_IVA         0x00fc
0118
0119 #ifndef __ASSEMBLER__
0120 /* Function prototypes */
0121 extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
0122 extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
0123
0124 int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data);
0125
0126 #endif
0127
0128 #endif