arm/mach-omap2/prm-regbits-44xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * OMAP44xx Power Management register bits
0004  *
0005  * Copyright (C) 2009-2010 Texas Instruments, Inc.
0006  * Copyright (C) 2009-2010 Nokia Corporation
0007  *
0008  * Paul Walmsley (paul@pwsan.com)
0009  * Rajendra Nayak (rnayak@ti.com)
0010  * Benoit Cousson (b-cousson@ti.com)
0011  *
0012  * This file is automatically generated from the OMAP hardware databases.
0013  * We respectfully ask that any modifications to this file be coordinated
0014  * with the public linux-omap@vger.kernel.org mailing list and the
0015  * authors above to ensure that the autogeneration scripts are kept
0016  * up-to-date with the file contents.
0017  */
0018
0019 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
0020 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
0021
0022 #define OMAP4430_C2C_RST_SHIFT                      10
0023 #define OMAP4430_CMDRA_VDD_CORE_L_MASK                  (0xff << 0)
0024 #define OMAP4430_CMDRA_VDD_IVA_L_MASK                   (0xff << 8)
0025 #define OMAP4430_CMDRA_VDD_MPU_L_MASK                   (0xff << 16)
0026 #define OMAP4430_DATA_SHIFT                     16
0027 #define OMAP4430_ERRORGAIN_MASK                     (0xff << 16)
0028 #define OMAP4430_ERROROFFSET_MASK                   (0xff << 24)
0029 #define OMAP4430_EXTERNAL_WARM_RST_SHIFT                5
0030 #define OMAP4430_FORCEUPDATE_MASK                   (1 << 1)
0031 #define OMAP4430_GLOBAL_COLD_RST_SHIFT                  0
0032 #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT               1
0033 #define OMAP4430_GLOBAL_WUEN_MASK                   (1 << 16)
0034 #define OMAP4430_HSMCODE_MASK                       (0x7 << 0)
0035 #define OMAP4430_SRMODEEN_MASK                      (1 << 4)
0036 #define OMAP4430_HSMODEEN_MASK                      (1 << 3)
0037 #define OMAP4430_HSSCLL_SHIFT                       24
0038 #define OMAP4430_ICEPICK_RST_SHIFT                  9
0039 #define OMAP4430_INITVDD_MASK                       (1 << 2)
0040 #define OMAP4430_INITVOLTAGE_MASK                   (0xff << 8)
0041 #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT                24
0042 #define OMAP4430_LASTPOWERSTATEENTERED_MASK             (0x3 << 24)
0043 #define OMAP4430_LOGICRETSTATE_SHIFT                    2
0044 #define OMAP4430_LOGICRETSTATE_MASK                 (1 << 2)
0045 #define OMAP4430_LOGICSTATEST_SHIFT                 2
0046 #define OMAP4430_LOGICSTATEST_MASK                  (1 << 2)
0047 #define OMAP4430_LOSTCONTEXT_DFF_MASK                   (1 << 0)
0048 #define OMAP4430_LOSTMEM_AESSMEM_MASK                   (1 << 8)
0049 #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT              4
0050 #define OMAP4430_LOWPOWERSTATECHANGE_MASK               (1 << 4)
0051 #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT                2
0052 #define OMAP4430_MPU_WDT_RST_SHIFT                  3
0053 #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK             (0x3 << 24)
0054 #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK                (1 << 12)
0055 #define OMAP4430_OCP_NRET_BANK_STATEST_MASK             (0x3 << 12)
0056 #define OMAP4430_OFF_SHIFT                      0
0057 #define OMAP4430_ON_SHIFT                       24
0058 #define OMAP4430_ON_MASK                        (0xff << 24)
0059 #define OMAP4430_ONLP_SHIFT                     16
0060 #define OMAP4430_RAMP_DOWN_COUNT_SHIFT                  16
0061 #define OMAP4430_RAMP_UP_COUNT_SHIFT                    0
0062 #define OMAP4430_RAMP_UP_PRESCAL_SHIFT                  8
0063 #define OMAP4430_REGADDR_SHIFT                      8
0064 #define OMAP4430_RET_SHIFT                      8
0065 #define OMAP4430_RST_GLOBAL_WARM_SW_MASK                (1 << 0)
0066 #define OMAP4430_SA_VDD_CORE_L_SHIFT                    0
0067 #define OMAP4430_SA_VDD_CORE_L_0_6_MASK                 (0x7f << 0)
0068 #define OMAP4430_SA_VDD_IVA_L_SHIFT                 8
0069 #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK           (0x7f << 8)
0070 #define OMAP4430_SA_VDD_MPU_L_SHIFT                 16
0071 #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK           (0x7f << 16)
0072 #define OMAP4430_SCLH_SHIFT                     0
0073 #define OMAP4430_SCLL_SHIFT                     8
0074 #define OMAP4430_SECURE_WDT_RST_SHIFT                   4
0075 #define OMAP4430_SLAVEADDR_SHIFT                    0
0076 #define OMAP4430_SMPSWAITTIMEMAX_SHIFT                  8
0077 #define OMAP4430_SMPSWAITTIMEMIN_SHIFT                  8
0078 #define OMAP4430_TIMEOUT_SHIFT                      0
0079 #define OMAP4430_TIMEOUTEN_MASK                     (1 << 3)
0080 #define OMAP4430_VALID_MASK                     (1 << 24)
0081 #define OMAP4430_VDDMAX_SHIFT                       24
0082 #define OMAP4430_VDDMIN_SHIFT                       16
0083 #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT                8
0084 #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT             7
0085 #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT             6
0086 #define OMAP4430_VOLRA_VDD_CORE_L_MASK                  (0xff << 0)
0087 #define OMAP4430_VOLRA_VDD_IVA_L_MASK                   (0xff << 8)
0088 #define OMAP4430_VOLRA_VDD_MPU_L_MASK                   (0xff << 16)
0089 #define OMAP4430_VPENABLE_MASK                      (1 << 0)
0090 #define OMAP4430_VPVOLTAGE_MASK                     (0xff << 0)
0091 #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK              (1 << 21)
0092 #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK               (1 << 29)
0093 #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK               (1 << 5)
0094 #define OMAP4430_VSTEPMAX_SHIFT                     0
0095 #define OMAP4430_VSTEPMIN_SHIFT                     0
0096 #define OMAP4430_WUCLK_CTRL_MASK                    (1 << 8)
0097 #define OMAP4430_WUCLK_STATUS_SHIFT                 9
0098 #define OMAP4430_WUCLK_STATUS_MASK                  (1 << 9)
0099 #endif