arm/mach-omap2/prm-regbits-34xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * OMAP3430 Power/Reset Management register bits
0004  *
0005  * Copyright (C) 2007-2008 Texas Instruments, Inc.
0006  * Copyright (C) 2007-2008 Nokia Corporation
0007  *
0008  * Written by Paul Walmsley
0009  */
0010 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
0011 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
0012
0013
0014 #include "prm3xxx.h"
0015
0016 #define OMAP3430_ERROROFFSET_MASK           (0xff << 24)
0017 #define OMAP3430_ERRORGAIN_MASK             (0xff << 16)
0018 #define OMAP3430_INITVOLTAGE_MASK           (0xff << 8)
0019 #define OMAP3430_TIMEOUTEN_MASK             (1 << 3)
0020 #define OMAP3430_INITVDD_MASK               (1 << 2)
0021 #define OMAP3430_FORCEUPDATE_MASK           (1 << 1)
0022 #define OMAP3430_VPENABLE_MASK              (1 << 0)
0023 #define OMAP3430_SMPSWAITTIMEMIN_SHIFT          8
0024 #define OMAP3430_VSTEPMIN_SHIFT             0
0025 #define OMAP3430_SMPSWAITTIMEMAX_SHIFT          8
0026 #define OMAP3430_VSTEPMAX_SHIFT             0
0027 #define OMAP3430_VDDMAX_SHIFT               24
0028 #define OMAP3430_VDDMIN_SHIFT               16
0029 #define OMAP3430_TIMEOUT_SHIFT              0
0030 #define OMAP3430_VPVOLTAGE_MASK             (0xff << 0)
0031 #define OMAP3430_EN_PER_SHIFT               7
0032 #define OMAP3430_LOGICSTATEST_MASK          (1 << 2)
0033 #define OMAP3430_LASTLOGICSTATEENTERED_MASK     (1 << 2)
0034 #define OMAP3430_LASTPOWERSTATEENTERED_MASK     (0x3 << 0)
0035 #define OMAP3430_GRPSEL_MCBSP5_MASK         (1 << 10)
0036 #define OMAP3430_GRPSEL_MCBSP1_MASK         (1 << 9)
0037 #define OMAP3630_GRPSEL_UART4_MASK          (1 << 18)
0038 #define OMAP3430_GRPSEL_GPIO6_MASK          (1 << 17)
0039 #define OMAP3430_GRPSEL_GPIO5_MASK          (1 << 16)
0040 #define OMAP3430_GRPSEL_GPIO4_MASK          (1 << 15)
0041 #define OMAP3430_GRPSEL_GPIO3_MASK          (1 << 14)
0042 #define OMAP3430_GRPSEL_GPIO2_MASK          (1 << 13)
0043 #define OMAP3430_GRPSEL_UART3_MASK          (1 << 11)
0044 #define OMAP3430_GRPSEL_GPT8_MASK           (1 << 9)
0045 #define OMAP3430_GRPSEL_GPT7_MASK           (1 << 8)
0046 #define OMAP3430_GRPSEL_GPT6_MASK           (1 << 7)
0047 #define OMAP3430_GRPSEL_GPT5_MASK           (1 << 6)
0048 #define OMAP3430_GRPSEL_MCBSP4_MASK         (1 << 2)
0049 #define OMAP3430_GRPSEL_MCBSP3_MASK         (1 << 1)
0050 #define OMAP3430_GRPSEL_MCBSP2_MASK         (1 << 0)
0051 #define OMAP3430_GRPSEL_GPIO1_MASK          (1 << 3)
0052 #define OMAP3430_GRPSEL_GPT12_MASK          (1 << 1)
0053 #define OMAP3430_GRPSEL_GPT1_MASK           (1 << 0)
0054 #define OMAP3430_RST3_IVA2_MASK             (1 << 2)
0055 #define OMAP3430_RST2_IVA2_MASK             (1 << 1)
0056 #define OMAP3430_RST1_IVA2_MASK             (1 << 0)
0057 #define OMAP3430_L2FLATMEMONSTATE_MASK          (0x3 << 22)
0058 #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK      (0x3 << 20)
0059 #define OMAP3430_L1FLATMEMONSTATE_MASK          (0x3 << 18)
0060 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK      (0x3 << 16)
0061 #define OMAP3430_L2FLATMEMRETSTATE_MASK         (1 << 11)
0062 #define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK     (1 << 10)
0063 #define OMAP3430_L1FLATMEMRETSTATE_MASK         (1 << 9)
0064 #define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK     (1 << 8)
0065 #define OMAP3430_L2FLATMEMSTATEST_MASK          (0x3 << 10)
0066 #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK      (0x3 << 8)
0067 #define OMAP3430_L1FLATMEMSTATEST_MASK          (0x3 << 6)
0068 #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK      (0x3 << 4)
0069 #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK         (0x3 << 10)
0070 #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK     (0x3 << 8)
0071 #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT        25
0072 #define OMAP3430_VP2_TRANXDONE_ST_MASK          (1 << 21)
0073 #define OMAP3430_VP1_TRANXDONE_ST_MASK          (1 << 15)
0074 #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT   8
0075 #define OMAP3430_MPU_DPLL_ST_SHIFT          7
0076 #define OMAP3430_PERIPH_DPLL_ST_SHIFT           6
0077 #define OMAP3430_CORE_DPLL_ST_SHIFT         5
0078 #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT      25
0079 #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8
0080 #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT            7
0081 #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT         6
0082 #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT           5
0083 #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT      5
0084 #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT     2
0085 #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK     (1 << 1)
0086 #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK      (1 << 0)
0087 #define OMAP3430_LASTMEM2STATEENTERED_MASK      (0x3 << 6)
0088 #define OMAP3430_LASTMEM1STATEENTERED_MASK      (0x3 << 4)
0089 #define OMAP3430_EN_IO_CHAIN_MASK           (1 << 16)
0090 #define OMAP3430_EN_IO_MASK             (1 << 8)
0091 #define OMAP3430_EN_GPIO1_MASK              (1 << 3)
0092 #define OMAP3430_ST_IO_CHAIN_MASK           (1 << 16)
0093 #define OMAP3430_ST_IO_MASK             (1 << 8)
0094 #define OMAP3430_SYS_CLKIN_SEL_SHIFT            0
0095 #define OMAP3430_SYS_CLKIN_SEL_WIDTH            3
0096 #define OMAP3430_CLKOUT_EN_SHIFT            7
0097 #define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK        (1 << 0)
0098 #define OMAP3430ES2_SAVEANDRESTORE_SHIFT        4
0099 #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT       16
0100 #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK        (0x7f << 16)
0101 #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT       0
0102 #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK        (0x7f << 0)
0103 #define OMAP3430_VOLRA1_MASK                (0xff << 16)
0104 #define OMAP3430_VOLRA0_MASK                (0xff << 0)
0105 #define OMAP3430_CMDRA1_MASK                (0xff << 16)
0106 #define OMAP3430_CMDRA0_MASK                (0xff << 0)
0107 #define OMAP3430_VC_CMD_ON_SHIFT            24
0108 #define OMAP3430_VC_CMD_ON_MASK             (0xFF << 24)
0109 #define OMAP3430_VC_CMD_ONLP_SHIFT          16
0110 #define OMAP3430_VC_CMD_RET_SHIFT           8
0111 #define OMAP3430_VC_CMD_OFF_SHIFT           0
0112 #define OMAP3430_SREN_MASK              (1 << 4)
0113 #define OMAP3430_HSEN_MASK              (1 << 3)
0114 #define OMAP3430_MCODE_MASK             (0x7 << 0)
0115 #define OMAP3430_VALID_MASK             (1 << 24)
0116 #define OMAP3430_DATA_SHIFT             16
0117 #define OMAP3430_REGADDR_SHIFT              8
0118 #define OMAP3430_SLAVEADDR_SHIFT            0
0119 #define OMAP3430_ICECRUSHER_RST_SHIFT           10
0120 #define OMAP3430_ICEPICK_RST_SHIFT          9
0121 #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT     8
0122 #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT     7
0123 #define OMAP3430_EXTERNAL_WARM_RST_SHIFT        6
0124 #define OMAP3430_SECURE_WD_RST_SHIFT            5
0125 #define OMAP3430_MPU_WD_RST_SHIFT           4
0126 #define OMAP3430_SECURITY_VIOL_RST_SHIFT        3
0127 #define OMAP3430_GLOBAL_SW_RST_SHIFT            1
0128 #define OMAP3430_GLOBAL_COLD_RST_SHIFT          0
0129 #define OMAP3430_GLOBAL_COLD_RST_MASK           (1 << 0)
0130 #define OMAP3430_PRM_VOLTCTRL_SEL_VMODE         (1 << 4)
0131 #define OMAP3430_PRM_VOLTCTRL_SEL_OFF           (1 << 3)
0132 #define OMAP3430_PRM_VOLTCTRL_AUTO_OFF          (1 << 2)
0133 #define OMAP3430_PRM_VOLTCTRL_AUTO_RET          (1 << 1)
0134 #define OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP        (1 << 0)
0135 #define OMAP3430_SETUP_TIME2_MASK           (0xffff << 16)
0136 #define OMAP3430_SETUP_TIME1_MASK           (0xffff << 0)
0137 #define OMAP3430_PRM_POLCTRL_OFFMODE_POL        (1 << 3)
0138 #define OMAP3430_PRM_POLCTRL_CLKOUT_POL         (1 << 2)
0139 #define OMAP3430_PRM_POLCTRL_CLKREQ_POL         (1 << 1)
0140 #define OMAP3430_PRM_POLCTRL_EXTVOL_POL         (1 << 0)
0141 #endif