arm/mach-omap2/prm-regbits-33xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * AM33XX PRM_XXX register bits
0004  *
0005  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
0006  */
0007
0008 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
0009 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
0010
0011 #include "prm.h"
0012
0013 #define AM33XX_GFX_MEM_ONSTATE_MASK         (0x3 << 17)
0014 #define AM33XX_GFX_MEM_RETSTATE_MASK            (1 << 6)
0015 #define AM33XX_GFX_MEM_STATEST_MASK         (0x3 << 4)
0016 #define AM33XX_GLOBAL_WARM_SW_RST_MASK          (1 << 1)
0017 #define AM33XX_RST_GLOBAL_WARM_SW_MASK          (1 << 0)
0018 #define AM33XX_PRUSS_MEM_ONSTATE_MASK           (0x3 << 5)
0019 #define AM33XX_PRUSS_MEM_RETSTATE_MASK          (1 << 7)
0020 #define AM33XX_PRUSS_MEM_STATEST_MASK           (0x3 << 23)
0021 #define AM33XX_LASTPOWERSTATEENTERED_SHIFT      24
0022 #define AM33XX_LASTPOWERSTATEENTERED_MASK       (0x3 << 24)
0023 #define AM33XX_LOGICRETSTATE_MASK           (1 << 2)
0024 #define AM33XX_LOGICRETSTATE_3_3_MASK           (1 << 3)
0025 #define AM33XX_LOGICSTATEST_SHIFT           2
0026 #define AM33XX_LOGICSTATEST_MASK            (1 << 2)
0027 #define AM33XX_LOWPOWERSTATECHANGE_SHIFT        4
0028 #define AM33XX_LOWPOWERSTATECHANGE_MASK         (1 << 4)
0029 #define AM33XX_MPU_L1_ONSTATE_MASK          (0x3 << 18)
0030 #define AM33XX_MPU_L1_RETSTATE_MASK         (1 << 22)
0031 #define AM33XX_MPU_L1_STATEST_MASK          (0x3 << 6)
0032 #define AM33XX_MPU_L2_ONSTATE_MASK          (0x3 << 20)
0033 #define AM33XX_MPU_L2_RETSTATE_MASK         (1 << 23)
0034 #define AM33XX_MPU_L2_STATEST_MASK          (0x3 << 8)
0035 #define AM33XX_MPU_RAM_ONSTATE_MASK         (0x3 << 16)
0036 #define AM33XX_MPU_RAM_RETSTATE_MASK            (1 << 24)
0037 #define AM33XX_MPU_RAM_STATEST_MASK         (0x3 << 4)
0038 #define AM33XX_PER_MEM_ONSTATE_MASK         (0x3 << 25)
0039 #define AM33XX_PER_MEM_RETSTATE_MASK            (1 << 29)
0040 #define AM33XX_PER_MEM_STATEST_MASK         (0x3 << 17)
0041 #define AM33XX_RAM_MEM_ONSTATE_MASK         (0x3 << 30)
0042 #define AM33XX_RAM_MEM_RETSTATE_MASK            (1 << 27)
0043 #define AM33XX_RAM_MEM_STATEST_MASK         (0x3 << 21)
0044 #endif