arm/mach-omap2/prcm_mpu7xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * DRA7xx PRCM MPU instance offset macros
0004  *
0005  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
0006  *
0007  * Generated by code originally written by:
0008  * Paul Walmsley (paul@pwsan.com)
0009  * Rajendra Nayak (rnayak@ti.com)
0010  * Benoit Cousson (b-cousson@ti.com)
0011  *
0012  * This file is automatically generated from the OMAP hardware databases.
0013  * We respectfully ask that any modifications to this file be coordinated
0014  * with the public linux-omap@vger.kernel.org mailing list and the
0015  * authors above to ensure that the autogeneration scripts are kept
0016  * up-to-date with the file contents.
0017  */
0018
0019 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
0020 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
0021
0022 #include "prcm_mpu_44xx_54xx.h"
0023
0024 #define DRA7XX_PRCM_MPU_BASE            0x48243000
0025
0026 #define DRA7XX_PRCM_MPU_REGADDR(inst, reg)              \
0027     OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
0028
0029 /* MPU_PRCM instances */
0030 #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
0031 #define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
0032 #define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
0033 #define DRA7XX_MPU_PRCM_CM_C0_INST  0x0600
0034 #define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
0035 #define DRA7XX_MPU_PRCM_CM_C1_INST  0x0a00
0036
0037 /* PRCM_MPU clockdomain register offsets (from instance start) */
0038 #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS   0x0000
0039 #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS   0x0000
0040
0041
0042 /* MPU_PRCM */
0043
0044 /* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */
0045 #define DRA7XX_REVISION_PRCM_MPU_OFFSET             0x0000
0046
0047 /* MPU_PRCM.PRCM_MPU_DEVICE register offsets */
0048 #define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET        0x0010
0049 #define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET   0x0014
0050
0051 /* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */
0052 #define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET             0x0000
0053 #define DRA7XX_PM_CPU0_PWRSTST_OFFSET               0x0004
0054 #define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET          0x0010
0055 #define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET            0x0014
0056 #define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET          0x0024
0057
0058 /* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */
0059 #define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET             0x0000
0060 #define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET          0x0020
0061 #define DRA7XX_CM_CPU0_CPU0_CLKCTRL             DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020)
0062
0063 /* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */
0064 #define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET             0x0000
0065 #define DRA7XX_PM_CPU1_PWRSTST_OFFSET               0x0004
0066 #define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET          0x0010
0067 #define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET            0x0014
0068 #define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET          0x0024
0069
0070 /* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */
0071 #define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET             0x0000
0072 #define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET          0x0020
0073 #define DRA7XX_CM_CPU1_CPU1_CLKCTRL             DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020)
0074
0075 #endif