arm/mach-omap2/prcm_mpu54xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * OMAP54xx PRCM MPU instance offset macros
0004  *
0005  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
0006  *
0007  * Paul Walmsley (paul@pwsan.com)
0008  * Rajendra Nayak (rnayak@ti.com)
0009  * Benoit Cousson (b-cousson@ti.com)
0010  *
0011  * This file is automatically generated from the OMAP hardware databases.
0012  * We respectfully ask that any modifications to this file be coordinated
0013  * with the public linux-omap@vger.kernel.org mailing list and the
0014  * authors above to ensure that the autogeneration scripts are kept
0015  * up-to-date with the file contents.
0016  */
0017
0018 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
0019 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
0020
0021 #include "prcm_mpu_44xx_54xx.h"
0022 #include "common.h"
0023
0024 #define OMAP54XX_PRCM_MPU_BASE          0x48243000
0025
0026 #define OMAP54XX_PRCM_MPU_REGADDR(inst, reg)                \
0027     OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))
0028
0029 /* PRCM_MPU instances */
0030 #define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST   0x0000
0031 #define OMAP54XX_PRCM_MPU_DEVICE_INST       0x0200
0032 #define OMAP54XX_PRCM_MPU_PRM_C0_INST       0x0400
0033 #define OMAP54XX_PRCM_MPU_CM_C0_INST        0x0600
0034 #define OMAP54XX_PRCM_MPU_PRM_C1_INST       0x0800
0035 #define OMAP54XX_PRCM_MPU_CM_C1_INST        0x0a00
0036
0037 /* PRCM_MPU clockdomain register offsets (from instance start) */
0038 #define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
0039 #define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
0040
0041
0042 /*
0043  * PRCM_MPU
0044  *
0045  * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
0046  * point of view the PRCM_MPU is a single entity. It shares the same
0047  * programming model as the global PRCM and thus can be assimilate as two new
0048  * MOD inside the PRCM
0049  */
0050
0051 /* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */
0052 #define OMAP54XX_REVISION_PRCM_MPU_OFFSET           0x0000
0053
0054 /* PRCM_MPU.PRCM_MPU_DEVICE register offsets */
0055 #define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET          0x0000
0056 #define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET        0x0004
0057 #define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET      0x0010
0058 #define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
0059
0060 /* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */
0061 #define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET           0x0000
0062 #define OMAP54XX_PM_CPU0_PWRSTST_OFFSET             0x0004
0063 #define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET            0x0010
0064 #define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET          0x0014
0065 #define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET            0x0024
0066
0067 /* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */
0068 #define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET           0x0000
0069 #define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET            0x0020
0070 #define OMAP54XX_CM_CPU0_CPU0_CLKCTRL               OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020)
0071
0072 /* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */
0073 #define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET           0x0000
0074 #define OMAP54XX_PM_CPU1_PWRSTST_OFFSET             0x0004
0075 #define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET            0x0010
0076 #define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET          0x0014
0077 #define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET            0x0024
0078
0079 /* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */
0080 #define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET           0x0000
0081 #define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET            0x0020
0082 #define OMAP54XX_CM_CPU1_CPU1_CLKCTRL               OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020)
0083
0084 #endif