arm/mach-omap2/prcm_mpu44xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * OMAP44xx PRCM MPU instance offset macros
0004  *
0005  * Copyright (C) 2010, 2012 Texas Instruments, Inc.
0006  * Copyright (C) 2010 Nokia Corporation
0007  *
0008  * Paul Walmsley (paul@pwsan.com)
0009  * Rajendra Nayak (rnayak@ti.com)
0010  * Benoit Cousson (b-cousson@ti.com)
0011  *
0012  * This file is automatically generated from the OMAP hardware databases.
0013  * We respectfully ask that any modifications to this file be coordinated
0014  * with the public linux-omap@vger.kernel.org mailing list and the
0015  * authors above to ensure that the autogeneration scripts are kept
0016  * up-to-date with the file contents.
0017  *
0018  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
0019  *     or "OMAP4430".
0020  */
0021
0022 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
0023 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
0024
0025 #include "prcm_mpu_44xx_54xx.h"
0026
0027 #define OMAP4430_PRCM_MPU_BASE          0x48243000
0028
0029 #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg)                \
0030     OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
0031
0032 /* PRCM_MPU instances */
0033 #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST  0x0000
0034 #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST   0x0200
0035 #define OMAP4430_PRCM_MPU_CPU0_INST     0x0400
0036 #define OMAP4430_PRCM_MPU_CPU1_INST     0x0800
0037
0038 /* PRCM_MPU clockdomain register offsets (from instance start) */
0039 #define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS  0x0018
0040 #define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS  0x0018
0041
0042
0043 /*
0044  * PRCM_MPU
0045  *
0046  * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
0047  * point of view the PRCM_MPU is a single entity. It shares the same
0048  * programming model as the global PRCM and thus can be assimilate as two new
0049  * MOD inside the PRCM
0050  */
0051
0052 /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
0053 #define OMAP4_REVISION_PRCM_OFFSET      0x0000
0054 #define OMAP4430_REVISION_PRCM          OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
0055
0056 /* PRCM_MPU.DEVICE_PRM register offsets */
0057 #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET     0x0000
0058 #define OMAP4430_PRCM_MPU_PRM_RSTST     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
0059 #define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET   0x0004
0060 #define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
0061
0062 /* PRCM_MPU.CPU0 register offsets */
0063 #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET      0x0000
0064 #define OMAP4430_PM_CPU0_PWRSTCTRL      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
0065 #define OMAP4_PM_CPU0_PWRSTST_OFFSET        0x0004
0066 #define OMAP4430_PM_CPU0_PWRSTST        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
0067 #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET   0x0008
0068 #define OMAP4430_RM_CPU0_CPU0_CONTEXT       OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
0069 #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET   0x000c
0070 #define OMAP4430_RM_CPU0_CPU0_RSTCTRL       OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
0071 #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET     0x0010
0072 #define OMAP4430_RM_CPU0_CPU0_RSTST     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
0073 #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET   0x0014
0074 #define OMAP4430_CM_CPU0_CPU0_CLKCTRL       OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
0075 #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET      0x0018
0076 #define OMAP4430_CM_CPU0_CLKSTCTRL      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
0077
0078 /* PRCM_MPU.CPU1 register offsets */
0079 #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET      0x0000
0080 #define OMAP4430_PM_CPU1_PWRSTCTRL      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
0081 #define OMAP4_PM_CPU1_PWRSTST_OFFSET        0x0004
0082 #define OMAP4430_PM_CPU1_PWRSTST        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
0083 #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET   0x0008
0084 #define OMAP4430_RM_CPU1_CPU1_CONTEXT       OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
0085 #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET   0x000c
0086 #define OMAP4430_RM_CPU1_CPU1_RSTCTRL       OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
0087 #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET     0x0010
0088 #define OMAP4430_RM_CPU1_CPU1_RSTST     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
0089 #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET   0x0014
0090 #define OMAP4430_CM_CPU1_CPU1_CLKCTRL       OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
0091 #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET      0x0018
0092 #define OMAP4430_CM_CPU1_CLKSTCTRL      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
0093
0094 #endif