arm/mach-omap2/prcm43xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * AM43x PRCM defines
0004  *
0005  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
0006  */
0007
0008 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
0009 #define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
0010
0011 #define AM43XX_PRM_PARTITION                1
0012 #define AM43XX_CM_PARTITION             1
0013
0014 /* PRM instances */
0015 #define AM43XX_PRM_OCP_SOCKET_INST          0x0000
0016 #define AM43XX_PRM_MPU_INST             0x0300
0017 #define AM43XX_PRM_GFX_INST             0x0400
0018 #define AM43XX_PRM_RTC_INST             0x0500
0019 #define AM43XX_PRM_TAMPER_INST              0x0600
0020 #define AM43XX_PRM_CEFUSE_INST              0x0700
0021 #define AM43XX_PRM_PER_INST             0x0800
0022 #define AM43XX_PRM_WKUP_INST                0x2000
0023 #define AM43XX_PRM_DEVICE_INST              0x4000
0024
0025 /* PRM_IRQ offsets */
0026 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET         0x0004
0027 #define AM43XX_PRM_IRQENABLE_MPU_OFFSET         0x0008
0028
0029 /* Other PRM offsets */
0030 #define AM43XX_PRM_IO_PMCTRL_OFFSET         0x0024
0031
0032 /* CM instances */
0033 #define AM43XX_CM_WKUP_INST             0x2800
0034 #define AM43XX_CM_MPU_INST              0x8300
0035 #define AM43XX_CM_GFX_INST              0x8400
0036 #define AM43XX_CM_RTC_INST              0x8500
0037 #define AM43XX_CM_TAMPER_INST               0x8600
0038 #define AM43XX_CM_CEFUSE_INST               0x8700
0039 #define AM43XX_CM_PER_INST              0x8800
0040
0041 /* CD offsets */
0042 #define AM43XX_CM_WKUP_L3_AON_CDOFFS            0x0000
0043 #define AM43XX_CM_WKUP_L3S_TSC_CDOFFS           0x0100
0044 #define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS       0x0200
0045 #define AM43XX_CM_WKUP_WKUP_CDOFFS          0x0300
0046 #define AM43XX_CM_MPU_MPU_CDOFFS            0x0000
0047 #define AM43XX_CM_GFX_GFX_L3_CDOFFS         0x0000
0048 #define AM43XX_CM_RTC_RTC_CDOFFS            0x0000
0049 #define AM43XX_CM_TAMPER_TAMPER_CDOFFS          0x0000
0050 #define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS          0x0000
0051 #define AM43XX_CM_PER_L3_CDOFFS             0x0000
0052 #define AM43XX_CM_PER_L3S_CDOFFS            0x0200
0053 #define AM43XX_CM_PER_ICSS_CDOFFS           0x0300
0054 #define AM43XX_CM_PER_L4LS_CDOFFS           0x0400
0055 #define AM43XX_CM_PER_EMIF_CDOFFS           0x0700
0056 #define AM43XX_CM_PER_LCDC_CDOFFS           0x0800
0057 #define AM43XX_CM_PER_DSS_CDOFFS            0x0a00
0058 #define AM43XX_CM_PER_CPSW_CDOFFS           0x0b00
0059 #define AM43XX_CM_PER_OCPWP_L3_CDOFFS           0x0c00
0060
0061 /* CLK CTRL offsets */
0062 #define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET        0x0020
0063 #define AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET       0x0720
0064
0065 #endif