arm/mach-omap2/powerdomains7xx_data.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * DRA7xx Power domains framework
0004  *
0005  * Copyright (C) 2009-2013 Texas Instruments, Inc.
0006  * Copyright (C) 2009-2011 Nokia Corporation
0007  *
0008  * Generated by code originally written by:
0009  * Abhijit Pagare (abhijitpagare@ti.com)
0010  * Benoit Cousson (b-cousson@ti.com)
0011  * Paul Walmsley (paul@pwsan.com)
0012  *
0013  * This file is automatically generated from the OMAP hardware databases.
0014  * We respectfully ask that any modifications to this file be coordinated
0015  * with the public linux-omap@vger.kernel.org mailing list and the
0016  * authors above to ensure that the autogeneration scripts are kept
0017  * up-to-date with the file contents.
0018  */
0019
0020 #include <linux/kernel.h>
0021 #include <linux/init.h>
0022
0023 #include "powerdomain.h"
0024
0025 #include "prcm-common.h"
0026 #include "prcm44xx.h"
0027 #include "prm7xx.h"
0028 #include "prcm_mpu7xx.h"
0029 #include "soc.h"
0030
0031 /* iva_7xx_pwrdm: IVA-HD power domain */
0032 static struct powerdomain iva_7xx_pwrdm = {
0033     .name         = "iva_pwrdm",
0034     .prcm_offs    = DRA7XX_PRM_IVA_INST,
0035     .prcm_partition   = DRA7XX_PRM_PARTITION,
0036     .pwrsts       = PWRSTS_OFF_ON,
0037     .banks        = 4,
0038     .pwrsts_mem_on  = {
0039         [0] = PWRSTS_ON,    /* hwa_mem */
0040         [1] = PWRSTS_ON,    /* sl2_mem */
0041         [2] = PWRSTS_ON,    /* tcm1_mem */
0042         [3] = PWRSTS_ON,    /* tcm2_mem */
0043     },
0044     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0045 };
0046
0047 /* rtc_7xx_pwrdm:  */
0048 static struct powerdomain rtc_7xx_pwrdm = {
0049     .name         = "rtc_pwrdm",
0050     .prcm_offs    = DRA7XX_PRM_RTC_INST,
0051     .prcm_partition   = DRA7XX_PRM_PARTITION,
0052     .pwrsts       = PWRSTS_ON,
0053 };
0054
0055 /* custefuse_7xx_pwrdm: Customer efuse controller power domain */
0056 static struct powerdomain custefuse_7xx_pwrdm = {
0057     .name         = "custefuse_pwrdm",
0058     .prcm_offs    = DRA7XX_PRM_CUSTEFUSE_INST,
0059     .prcm_partition   = DRA7XX_PRM_PARTITION,
0060     .pwrsts       = PWRSTS_OFF_ON,
0061     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0062 };
0063
0064 /* custefuse_aon_7xx_pwrdm: Customer efuse controller power domain */
0065 static struct powerdomain custefuse_aon_7xx_pwrdm = {
0066     .name         = "custefuse_pwrdm",
0067     .prcm_offs    = DRA7XX_PRM_CUSTEFUSE_INST,
0068     .prcm_partition   = DRA7XX_PRM_PARTITION,
0069     .pwrsts       = PWRSTS_ON,
0070 };
0071
0072 /* ipu_7xx_pwrdm: Audio back end power domain */
0073 static struct powerdomain ipu_7xx_pwrdm = {
0074     .name         = "ipu_pwrdm",
0075     .prcm_offs    = DRA7XX_PRM_IPU_INST,
0076     .prcm_partition   = DRA7XX_PRM_PARTITION,
0077     .pwrsts       = PWRSTS_OFF_ON,
0078     .banks        = 2,
0079     .pwrsts_mem_on  = {
0080         [0] = PWRSTS_ON,    /* aessmem */
0081         [1] = PWRSTS_ON,    /* periphmem */
0082     },
0083     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0084 };
0085
0086 /* dss_7xx_pwrdm: Display subsystem power domain */
0087 static struct powerdomain dss_7xx_pwrdm = {
0088     .name         = "dss_pwrdm",
0089     .prcm_offs    = DRA7XX_PRM_DSS_INST,
0090     .prcm_partition   = DRA7XX_PRM_PARTITION,
0091     .pwrsts       = PWRSTS_OFF_ON,
0092     .banks        = 1,
0093     .pwrsts_mem_on  = {
0094         [0] = PWRSTS_ON,    /* dss_mem */
0095     },
0096     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0097 };
0098
0099 /* l4per_7xx_pwrdm: Target peripherals power domain */
0100 static struct powerdomain l4per_7xx_pwrdm = {
0101     .name         = "l4per_pwrdm",
0102     .prcm_offs    = DRA7XX_PRM_L4PER_INST,
0103     .prcm_partition   = DRA7XX_PRM_PARTITION,
0104     .pwrsts       = PWRSTS_ON,
0105     .banks        = 2,
0106     .pwrsts_mem_on  = {
0107         [0] = PWRSTS_ON,    /* nonretained_bank */
0108         [1] = PWRSTS_ON,    /* retained_bank */
0109     },
0110     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0111 };
0112
0113 /* gpu_7xx_pwrdm: 3D accelerator power domain */
0114 static struct powerdomain gpu_7xx_pwrdm = {
0115     .name         = "gpu_pwrdm",
0116     .prcm_offs    = DRA7XX_PRM_GPU_INST,
0117     .prcm_partition   = DRA7XX_PRM_PARTITION,
0118     .pwrsts       = PWRSTS_OFF_ON,
0119     .banks        = 1,
0120     .pwrsts_mem_on  = {
0121         [0] = PWRSTS_ON,    /* gpu_mem */
0122     },
0123     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0124 };
0125
0126 /* wkupaon_7xx_pwrdm: Wake-up power domain */
0127 static struct powerdomain wkupaon_7xx_pwrdm = {
0128     .name         = "wkupaon_pwrdm",
0129     .prcm_offs    = DRA7XX_PRM_WKUPAON_INST,
0130     .prcm_partition   = DRA7XX_PRM_PARTITION,
0131     .pwrsts       = PWRSTS_ON,
0132     .banks        = 1,
0133     .pwrsts_mem_on  = {
0134         [0] = PWRSTS_ON,    /* wkup_bank */
0135     },
0136 };
0137
0138 /* core_7xx_pwrdm: CORE power domain */
0139 static struct powerdomain core_7xx_pwrdm = {
0140     .name         = "core_pwrdm",
0141     .prcm_offs    = DRA7XX_PRM_CORE_INST,
0142     .prcm_partition   = DRA7XX_PRM_PARTITION,
0143     .pwrsts       = PWRSTS_ON,
0144     .banks        = 5,
0145     .pwrsts_mem_on  = {
0146         [0] = PWRSTS_ON,    /* core_nret_bank */
0147         [1] = PWRSTS_ON,    /* core_ocmram */
0148         [2] = PWRSTS_ON,    /* core_other_bank */
0149         [3] = PWRSTS_ON,    /* ipu_l2ram */
0150         [4] = PWRSTS_ON,    /* ipu_unicache */
0151     },
0152     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0153 };
0154
0155 /* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
0156 static struct powerdomain coreaon_7xx_pwrdm = {
0157     .name         = "coreaon_pwrdm",
0158     .prcm_offs    = DRA7XX_PRM_COREAON_INST,
0159     .prcm_partition   = DRA7XX_PRM_PARTITION,
0160     .pwrsts       = PWRSTS_ON,
0161 };
0162
0163 /* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
0164 static struct powerdomain cpu0_7xx_pwrdm = {
0165     .name         = "cpu0_pwrdm",
0166     .prcm_offs    = DRA7XX_MPU_PRCM_PRM_C0_INST,
0167     .prcm_partition   = DRA7XX_MPU_PRCM_PARTITION,
0168     .pwrsts       = PWRSTS_RET_ON,
0169     .pwrsts_logic_ret = PWRSTS_RET,
0170     .banks        = 1,
0171     .pwrsts_mem_ret = {
0172         [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
0173     },
0174     .pwrsts_mem_on  = {
0175         [0] = PWRSTS_ON,    /* cpu0_l1 */
0176     },
0177 };
0178
0179 /* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
0180 static struct powerdomain cpu1_7xx_pwrdm = {
0181     .name         = "cpu1_pwrdm",
0182     .prcm_offs    = DRA7XX_MPU_PRCM_PRM_C1_INST,
0183     .prcm_partition   = DRA7XX_MPU_PRCM_PARTITION,
0184     .pwrsts       = PWRSTS_RET_ON,
0185     .pwrsts_logic_ret = PWRSTS_RET,
0186     .banks        = 1,
0187     .pwrsts_mem_ret = {
0188         [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
0189     },
0190     .pwrsts_mem_on  = {
0191         [0] = PWRSTS_ON,    /* cpu1_l1 */
0192     },
0193 };
0194
0195 /* vpe_7xx_pwrdm:  */
0196 static struct powerdomain vpe_7xx_pwrdm = {
0197     .name         = "vpe_pwrdm",
0198     .prcm_offs    = DRA7XX_PRM_VPE_INST,
0199     .prcm_partition   = DRA7XX_PRM_PARTITION,
0200     .pwrsts       = PWRSTS_OFF_ON,
0201     .banks        = 1,
0202     .pwrsts_mem_on  = {
0203         [0] = PWRSTS_ON,    /* vpe_bank */
0204     },
0205     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0206 };
0207
0208 /* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
0209 static struct powerdomain mpu_7xx_pwrdm = {
0210     .name         = "mpu_pwrdm",
0211     .prcm_offs    = DRA7XX_PRM_MPU_INST,
0212     .prcm_partition   = DRA7XX_PRM_PARTITION,
0213     .pwrsts       = PWRSTS_RET_ON,
0214     .pwrsts_logic_ret = PWRSTS_RET,
0215     .banks        = 2,
0216     .pwrsts_mem_ret = {
0217         [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
0218         [1] = PWRSTS_RET,   /* mpu_ram */
0219     },
0220     .pwrsts_mem_on  = {
0221         [0] = PWRSTS_ON,    /* mpu_l2 */
0222         [1] = PWRSTS_ON,    /* mpu_ram */
0223     },
0224 };
0225
0226 /* l3init_7xx_pwrdm: L3 initators pheripherals power domain  */
0227 static struct powerdomain l3init_7xx_pwrdm = {
0228     .name         = "l3init_pwrdm",
0229     .prcm_offs    = DRA7XX_PRM_L3INIT_INST,
0230     .prcm_partition   = DRA7XX_PRM_PARTITION,
0231     .pwrsts       = PWRSTS_ON,
0232     .banks        = 3,
0233     .pwrsts_mem_on  = {
0234         [0] = PWRSTS_ON,    /* gmac_bank */
0235         [1] = PWRSTS_ON,    /* l3init_bank1 */
0236         [2] = PWRSTS_ON,    /* l3init_bank2 */
0237     },
0238     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0239 };
0240
0241 /* eve3_7xx_pwrdm:  */
0242 static struct powerdomain eve3_7xx_pwrdm = {
0243     .name         = "eve3_pwrdm",
0244     .prcm_offs    = DRA7XX_PRM_EVE3_INST,
0245     .prcm_partition   = DRA7XX_PRM_PARTITION,
0246     .pwrsts       = PWRSTS_OFF_ON,
0247     .banks        = 1,
0248     .pwrsts_mem_on  = {
0249         [0] = PWRSTS_ON,    /* eve3_bank */
0250     },
0251     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0252 };
0253
0254 /* emu_7xx_pwrdm: Emulation power domain */
0255 static struct powerdomain emu_7xx_pwrdm = {
0256     .name         = "emu_pwrdm",
0257     .prcm_offs    = DRA7XX_PRM_EMU_INST,
0258     .prcm_partition   = DRA7XX_PRM_PARTITION,
0259     .pwrsts       = PWRSTS_OFF_ON,
0260     .banks        = 1,
0261     .pwrsts_mem_on  = {
0262         [0] = PWRSTS_ON,    /* emu_bank */
0263     },
0264 };
0265
0266 /* dsp2_7xx_pwrdm:  */
0267 static struct powerdomain dsp2_7xx_pwrdm = {
0268     .name         = "dsp2_pwrdm",
0269     .prcm_offs    = DRA7XX_PRM_DSP2_INST,
0270     .prcm_partition   = DRA7XX_PRM_PARTITION,
0271     .pwrsts       = PWRSTS_OFF_ON,
0272     .banks        = 3,
0273     .pwrsts_mem_on  = {
0274         [0] = PWRSTS_ON,    /* dsp2_edma */
0275         [1] = PWRSTS_ON,    /* dsp2_l1 */
0276         [2] = PWRSTS_ON,    /* dsp2_l2 */
0277     },
0278     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0279 };
0280
0281 /* dsp1_7xx_pwrdm: Tesla processor power domain */
0282 static struct powerdomain dsp1_7xx_pwrdm = {
0283     .name         = "dsp1_pwrdm",
0284     .prcm_offs    = DRA7XX_PRM_DSP1_INST,
0285     .prcm_partition   = DRA7XX_PRM_PARTITION,
0286     .pwrsts       = PWRSTS_OFF_ON,
0287     .banks        = 3,
0288     .pwrsts_mem_on  = {
0289         [0] = PWRSTS_ON,    /* dsp1_edma */
0290         [1] = PWRSTS_ON,    /* dsp1_l1 */
0291         [2] = PWRSTS_ON,    /* dsp1_l2 */
0292     },
0293     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0294 };
0295
0296 /* cam_7xx_pwrdm: Camera subsystem power domain */
0297 static struct powerdomain cam_7xx_pwrdm = {
0298     .name         = "cam_pwrdm",
0299     .prcm_offs    = DRA7XX_PRM_CAM_INST,
0300     .prcm_partition   = DRA7XX_PRM_PARTITION,
0301     .pwrsts       = PWRSTS_OFF_ON,
0302     .banks        = 1,
0303     .pwrsts_mem_on  = {
0304         [0] = PWRSTS_ON,    /* vip_bank */
0305     },
0306     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0307 };
0308
0309 /* eve4_7xx_pwrdm:  */
0310 static struct powerdomain eve4_7xx_pwrdm = {
0311     .name         = "eve4_pwrdm",
0312     .prcm_offs    = DRA7XX_PRM_EVE4_INST,
0313     .prcm_partition   = DRA7XX_PRM_PARTITION,
0314     .pwrsts       = PWRSTS_OFF_ON,
0315     .banks        = 1,
0316     .pwrsts_mem_on  = {
0317         [0] = PWRSTS_ON,    /* eve4_bank */
0318     },
0319     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0320 };
0321
0322 /* eve2_7xx_pwrdm:  */
0323 static struct powerdomain eve2_7xx_pwrdm = {
0324     .name         = "eve2_pwrdm",
0325     .prcm_offs    = DRA7XX_PRM_EVE2_INST,
0326     .prcm_partition   = DRA7XX_PRM_PARTITION,
0327     .pwrsts       = PWRSTS_OFF_ON,
0328     .banks        = 1,
0329     .pwrsts_mem_on  = {
0330         [0] = PWRSTS_ON,    /* eve2_bank */
0331     },
0332     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0333 };
0334
0335 /* eve1_7xx_pwrdm:  */
0336 static struct powerdomain eve1_7xx_pwrdm = {
0337     .name         = "eve1_pwrdm",
0338     .prcm_offs    = DRA7XX_PRM_EVE1_INST,
0339     .prcm_partition   = DRA7XX_PRM_PARTITION,
0340     .pwrsts       = PWRSTS_OFF_ON,
0341     .banks        = 1,
0342     .pwrsts_mem_on  = {
0343         [0] = PWRSTS_ON,    /* eve1_bank */
0344     },
0345     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0346 };
0347
0348 /*
0349  * The following power domains are not under SW control
0350  *
0351  * mpuaon
0352  * mmaon
0353  */
0354
0355 /* As powerdomains are added or removed above, this list must also be changed */
0356 static struct powerdomain *powerdomains_dra7xx[] __initdata = {
0357     &iva_7xx_pwrdm,
0358     &rtc_7xx_pwrdm,
0359     &ipu_7xx_pwrdm,
0360     &dss_7xx_pwrdm,
0361     &l4per_7xx_pwrdm,
0362     &gpu_7xx_pwrdm,
0363     &wkupaon_7xx_pwrdm,
0364     &core_7xx_pwrdm,
0365     &coreaon_7xx_pwrdm,
0366     &cpu0_7xx_pwrdm,
0367     &cpu1_7xx_pwrdm,
0368     &vpe_7xx_pwrdm,
0369     &mpu_7xx_pwrdm,
0370     &l3init_7xx_pwrdm,
0371     &eve3_7xx_pwrdm,
0372     &emu_7xx_pwrdm,
0373     &dsp2_7xx_pwrdm,
0374     &dsp1_7xx_pwrdm,
0375     &cam_7xx_pwrdm,
0376     &eve4_7xx_pwrdm,
0377     &eve2_7xx_pwrdm,
0378     &eve1_7xx_pwrdm,
0379     NULL
0380 };
0381
0382 static struct powerdomain *powerdomains_dra76x[] __initdata = {
0383     &custefuse_aon_7xx_pwrdm,
0384     NULL
0385 };
0386
0387 static struct powerdomain *powerdomains_dra74x[] __initdata = {
0388     &custefuse_7xx_pwrdm,
0389     NULL
0390 };
0391
0392 static struct powerdomain *powerdomains_dra72x[] __initdata = {
0393     &custefuse_aon_7xx_pwrdm,
0394     NULL
0395 };
0396
0397 void __init dra7xx_powerdomains_init(void)
0398 {
0399     pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
0400     pwrdm_register_pwrdms(powerdomains_dra7xx);
0401
0402     if (soc_is_dra76x())
0403         pwrdm_register_pwrdms(powerdomains_dra76x);
0404     else if (soc_is_dra74x())
0405         pwrdm_register_pwrdms(powerdomains_dra74x);
0406     else if (soc_is_dra72x())
0407         pwrdm_register_pwrdms(powerdomains_dra72x);
0408
0409     pwrdm_complete_init();
0410 }