arm/mach-omap2/powerdomains54xx_data.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * OMAP54XX Power domains framework
0004  *
0005  * Copyright (C) 2013 Texas Instruments, Inc.
0006  *
0007  * Abhijit Pagare (abhijitpagare@ti.com)
0008  * Benoit Cousson (b-cousson@ti.com)
0009  * Paul Walmsley (paul@pwsan.com)
0010  *
0011  * This file is automatically generated from the OMAP hardware databases.
0012  * We respectfully ask that any modifications to this file be coordinated
0013  * with the public linux-omap@vger.kernel.org mailing list and the
0014  * authors above to ensure that the autogeneration scripts are kept
0015  * up-to-date with the file contents.
0016  */
0017
0018 #include <linux/kernel.h>
0019 #include <linux/init.h>
0020
0021 #include "powerdomain.h"
0022
0023 #include "prcm-common.h"
0024 #include "prcm44xx.h"
0025 #include "prm54xx.h"
0026 #include "prcm_mpu54xx.h"
0027
0028 /* core_54xx_pwrdm: CORE power domain */
0029 static struct powerdomain core_54xx_pwrdm = {
0030     .name         = "core_pwrdm",
0031     .voltdm       = { .name = "core" },
0032     .prcm_offs    = OMAP54XX_PRM_CORE_INST,
0033     .prcm_partition   = OMAP54XX_PRM_PARTITION,
0034     .pwrsts       = PWRSTS_RET_ON,
0035     .pwrsts_logic_ret = PWRSTS_RET,
0036     .banks        = 5,
0037     .pwrsts_mem_ret = {
0038         [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
0039         [1] = PWRSTS_OFF_RET,   /* core_ocmram */
0040         [2] = PWRSTS_OFF_RET,   /* core_other_bank */
0041         [3] = PWRSTS_OFF_RET,   /* ipu_l2ram */
0042         [4] = PWRSTS_OFF_RET,   /* ipu_unicache */
0043     },
0044     .pwrsts_mem_on  = {
0045         [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
0046         [1] = PWRSTS_OFF_RET,   /* core_ocmram */
0047         [2] = PWRSTS_OFF_RET,   /* core_other_bank */
0048         [3] = PWRSTS_OFF_RET,   /* ipu_l2ram */
0049         [4] = PWRSTS_OFF_RET,   /* ipu_unicache */
0050     },
0051     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0052 };
0053
0054 /* abe_54xx_pwrdm: Audio back end power domain */
0055 static struct powerdomain abe_54xx_pwrdm = {
0056     .name         = "abe_pwrdm",
0057     .voltdm       = { .name = "core" },
0058     .prcm_offs    = OMAP54XX_PRM_ABE_INST,
0059     .prcm_partition   = OMAP54XX_PRM_PARTITION,
0060     .pwrsts       = PWRSTS_OFF_RET_ON,
0061     .pwrsts_logic_ret = PWRSTS_OFF,
0062     .banks        = 2,
0063     .pwrsts_mem_ret = {
0064         [0] = PWRSTS_OFF_RET,   /* aessmem */
0065         [1] = PWRSTS_OFF_RET,   /* periphmem */
0066     },
0067     .pwrsts_mem_on  = {
0068         [0] = PWRSTS_OFF_RET,   /* aessmem */
0069         [1] = PWRSTS_OFF_RET,   /* periphmem */
0070     },
0071     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0072 };
0073
0074 /* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
0075 static struct powerdomain coreaon_54xx_pwrdm = {
0076     .name         = "coreaon_pwrdm",
0077     .voltdm       = { .name = "core" },
0078     .prcm_offs    = OMAP54XX_PRM_COREAON_INST,
0079     .prcm_partition   = OMAP54XX_PRM_PARTITION,
0080     .pwrsts       = PWRSTS_ON,
0081 };
0082
0083 /* dss_54xx_pwrdm: Display subsystem power domain */
0084 static struct powerdomain dss_54xx_pwrdm = {
0085     .name         = "dss_pwrdm",
0086     .voltdm       = { .name = "core" },
0087     .prcm_offs    = OMAP54XX_PRM_DSS_INST,
0088     .prcm_partition   = OMAP54XX_PRM_PARTITION,
0089     .pwrsts       = PWRSTS_OFF_RET_ON,
0090     .pwrsts_logic_ret = PWRSTS_OFF,
0091     .banks        = 1,
0092     .pwrsts_mem_ret = {
0093         [0] = PWRSTS_OFF_RET,   /* dss_mem */
0094     },
0095     .pwrsts_mem_on  = {
0096         [0] = PWRSTS_OFF_RET,   /* dss_mem */
0097     },
0098     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0099 };
0100
0101 /* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
0102 static struct powerdomain cpu0_54xx_pwrdm = {
0103     .name         = "cpu0_pwrdm",
0104     .voltdm       = { .name = "mpu" },
0105     .prcm_offs    = OMAP54XX_PRCM_MPU_PRM_C0_INST,
0106     .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
0107     .pwrsts       = PWRSTS_RET_ON,
0108     .pwrsts_logic_ret = PWRSTS_RET,
0109     .banks        = 1,
0110     .pwrsts_mem_ret = {
0111         [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
0112     },
0113     .pwrsts_mem_on  = {
0114         [0] = PWRSTS_ON,    /* cpu0_l1 */
0115     },
0116 };
0117
0118 /* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
0119 static struct powerdomain cpu1_54xx_pwrdm = {
0120     .name         = "cpu1_pwrdm",
0121     .voltdm       = { .name = "mpu" },
0122     .prcm_offs    = OMAP54XX_PRCM_MPU_PRM_C1_INST,
0123     .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
0124     .pwrsts       = PWRSTS_RET_ON,
0125     .pwrsts_logic_ret = PWRSTS_RET,
0126     .banks        = 1,
0127     .pwrsts_mem_ret = {
0128         [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
0129     },
0130     .pwrsts_mem_on  = {
0131         [0] = PWRSTS_ON,    /* cpu1_l1 */
0132     },
0133 };
0134
0135 /* emu_54xx_pwrdm: Emulation power domain */
0136 static struct powerdomain emu_54xx_pwrdm = {
0137     .name         = "emu_pwrdm",
0138     .voltdm       = { .name = "wkup" },
0139     .prcm_offs    = OMAP54XX_PRM_EMU_INST,
0140     .prcm_partition   = OMAP54XX_PRM_PARTITION,
0141     .pwrsts       = PWRSTS_OFF_ON,
0142     .banks        = 1,
0143     .pwrsts_mem_ret = {
0144         [0] = PWRSTS_OFF_RET,   /* emu_bank */
0145     },
0146     .pwrsts_mem_on  = {
0147         [0] = PWRSTS_OFF_RET,   /* emu_bank */
0148     },
0149 };
0150
0151 /* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
0152 static struct powerdomain mpu_54xx_pwrdm = {
0153     .name         = "mpu_pwrdm",
0154     .voltdm       = { .name = "mpu" },
0155     .prcm_offs    = OMAP54XX_PRM_MPU_INST,
0156     .prcm_partition   = OMAP54XX_PRM_PARTITION,
0157     .pwrsts       = PWRSTS_RET_ON,
0158     .pwrsts_logic_ret = PWRSTS_RET,
0159     .banks        = 2,
0160     .pwrsts_mem_ret = {
0161         [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
0162         [1] = PWRSTS_RET,   /* mpu_ram */
0163     },
0164     .pwrsts_mem_on  = {
0165         [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
0166         [1] = PWRSTS_OFF_RET,   /* mpu_ram */
0167     },
0168 };
0169
0170 /* custefuse_54xx_pwrdm: Customer efuse controller power domain */
0171 static struct powerdomain custefuse_54xx_pwrdm = {
0172     .name         = "custefuse_pwrdm",
0173     .voltdm       = { .name = "core" },
0174     .prcm_offs    = OMAP54XX_PRM_CUSTEFUSE_INST,
0175     .prcm_partition   = OMAP54XX_PRM_PARTITION,
0176     .pwrsts       = PWRSTS_OFF_ON,
0177     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0178 };
0179
0180 /* dsp_54xx_pwrdm: Tesla processor power domain */
0181 static struct powerdomain dsp_54xx_pwrdm = {
0182     .name         = "dsp_pwrdm",
0183     .voltdm       = { .name = "mm" },
0184     .prcm_offs    = OMAP54XX_PRM_DSP_INST,
0185     .prcm_partition   = OMAP54XX_PRM_PARTITION,
0186     .pwrsts       = PWRSTS_OFF_RET_ON,
0187     .pwrsts_logic_ret = PWRSTS_OFF_RET,
0188     .banks        = 3,
0189     .pwrsts_mem_ret = {
0190         [0] = PWRSTS_OFF_RET,   /* dsp_edma */
0191         [1] = PWRSTS_OFF_RET,   /* dsp_l1 */
0192         [2] = PWRSTS_OFF_RET,   /* dsp_l2 */
0193     },
0194     .pwrsts_mem_on  = {
0195         [0] = PWRSTS_OFF_RET,   /* dsp_edma */
0196         [1] = PWRSTS_OFF_RET,   /* dsp_l1 */
0197         [2] = PWRSTS_OFF_RET,   /* dsp_l2 */
0198     },
0199     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0200 };
0201
0202 /* cam_54xx_pwrdm: Camera subsystem power domain */
0203 static struct powerdomain cam_54xx_pwrdm = {
0204     .name         = "cam_pwrdm",
0205     .voltdm       = { .name = "core" },
0206     .prcm_offs    = OMAP54XX_PRM_CAM_INST,
0207     .prcm_partition   = OMAP54XX_PRM_PARTITION,
0208     .pwrsts       = PWRSTS_OFF_ON,
0209     .banks        = 1,
0210     .pwrsts_mem_ret = {
0211         [0] = PWRSTS_OFF_RET,   /* cam_mem */
0212     },
0213     .pwrsts_mem_on  = {
0214         [0] = PWRSTS_OFF_RET,   /* cam_mem */
0215     },
0216     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0217 };
0218
0219 /* l3init_54xx_pwrdm: L3 initators pheripherals power domain  */
0220 static struct powerdomain l3init_54xx_pwrdm = {
0221     .name         = "l3init_pwrdm",
0222     .voltdm       = { .name = "core" },
0223     .prcm_offs    = OMAP54XX_PRM_L3INIT_INST,
0224     .prcm_partition   = OMAP54XX_PRM_PARTITION,
0225     .pwrsts       = PWRSTS_RET_ON,
0226     .pwrsts_logic_ret = PWRSTS_OFF_RET,
0227     .banks        = 2,
0228     .pwrsts_mem_ret = {
0229         [0] = PWRSTS_OFF_RET,   /* l3init_bank1 */
0230         [1] = PWRSTS_OFF_RET,   /* l3init_bank2 */
0231     },
0232     .pwrsts_mem_on  = {
0233         [0] = PWRSTS_OFF_RET,   /* l3init_bank1 */
0234         [1] = PWRSTS_OFF_RET,   /* l3init_bank2 */
0235     },
0236     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0237 };
0238
0239 /* gpu_54xx_pwrdm: 3D accelerator power domain */
0240 static struct powerdomain gpu_54xx_pwrdm = {
0241     .name         = "gpu_pwrdm",
0242     .voltdm       = { .name = "mm" },
0243     .prcm_offs    = OMAP54XX_PRM_GPU_INST,
0244     .prcm_partition   = OMAP54XX_PRM_PARTITION,
0245     .pwrsts       = PWRSTS_OFF_ON,
0246     .banks        = 1,
0247     .pwrsts_mem_ret = {
0248         [0] = PWRSTS_OFF_RET,   /* gpu_mem */
0249     },
0250     .pwrsts_mem_on  = {
0251         [0] = PWRSTS_OFF_RET,   /* gpu_mem */
0252     },
0253     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0254 };
0255
0256 /* wkupaon_54xx_pwrdm: Wake-up power domain */
0257 static struct powerdomain wkupaon_54xx_pwrdm = {
0258     .name         = "wkupaon_pwrdm",
0259     .voltdm       = { .name = "wkup" },
0260     .prcm_offs    = OMAP54XX_PRM_WKUPAON_INST,
0261     .prcm_partition   = OMAP54XX_PRM_PARTITION,
0262     .pwrsts       = PWRSTS_ON,
0263     .banks        = 1,
0264     .pwrsts_mem_ret = {
0265     },
0266     .pwrsts_mem_on  = {
0267         [0] = PWRSTS_ON,    /* wkup_bank */
0268     },
0269 };
0270
0271 /* iva_54xx_pwrdm: IVA-HD power domain */
0272 static struct powerdomain iva_54xx_pwrdm = {
0273     .name         = "iva_pwrdm",
0274     .voltdm       = { .name = "mm" },
0275     .prcm_offs    = OMAP54XX_PRM_IVA_INST,
0276     .prcm_partition   = OMAP54XX_PRM_PARTITION,
0277     .pwrsts       = PWRSTS_OFF_RET_ON,
0278     .pwrsts_logic_ret = PWRSTS_OFF,
0279     .banks        = 4,
0280     .pwrsts_mem_ret = {
0281         [0] = PWRSTS_OFF_RET,   /* hwa_mem */
0282         [1] = PWRSTS_OFF_RET,   /* sl2_mem */
0283         [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
0284         [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
0285     },
0286     .pwrsts_mem_on  = {
0287         [0] = PWRSTS_OFF_RET,   /* hwa_mem */
0288         [1] = PWRSTS_OFF_RET,   /* sl2_mem */
0289         [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
0290         [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
0291     },
0292     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0293 };
0294
0295 /*
0296  * The following power domains are not under SW control
0297  *
0298  * mpuaon
0299  * mmaon
0300  */
0301
0302 /* As powerdomains are added or removed above, this list must also be changed */
0303 static struct powerdomain *powerdomains_omap54xx[] __initdata = {
0304     &core_54xx_pwrdm,
0305     &abe_54xx_pwrdm,
0306     &coreaon_54xx_pwrdm,
0307     &dss_54xx_pwrdm,
0308     &cpu0_54xx_pwrdm,
0309     &cpu1_54xx_pwrdm,
0310     &emu_54xx_pwrdm,
0311     &mpu_54xx_pwrdm,
0312     &custefuse_54xx_pwrdm,
0313     &dsp_54xx_pwrdm,
0314     &cam_54xx_pwrdm,
0315     &l3init_54xx_pwrdm,
0316     &gpu_54xx_pwrdm,
0317     &wkupaon_54xx_pwrdm,
0318     &iva_54xx_pwrdm,
0319     NULL
0320 };
0321
0322 void __init omap54xx_powerdomains_init(void)
0323 {
0324     pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
0325     pwrdm_register_pwrdms(powerdomains_omap54xx);
0326     pwrdm_complete_init();
0327 }