arm/mach-omap2/powerdomains44xx_data.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * OMAP4 Power domains framework
0004  *
0005  * Copyright (C) 2009-2011 Texas Instruments, Inc.
0006  * Copyright (C) 2009-2011 Nokia Corporation
0007  *
0008  * Abhijit Pagare (abhijitpagare@ti.com)
0009  * Benoit Cousson (b-cousson@ti.com)
0010  * Paul Walmsley (paul@pwsan.com)
0011  *
0012  * This file is automatically generated from the OMAP hardware databases.
0013  * We respectfully ask that any modifications to this file be coordinated
0014  * with the public linux-omap@vger.kernel.org mailing list and the
0015  * authors above to ensure that the autogeneration scripts are kept
0016  * up-to-date with the file contents.
0017  */
0018
0019 #include <linux/kernel.h>
0020 #include <linux/init.h>
0021
0022 #include "powerdomain.h"
0023
0024 #include "prcm-common.h"
0025 #include "prcm44xx.h"
0026 #include "prm-regbits-44xx.h"
0027 #include "prm44xx.h"
0028 #include "prcm_mpu44xx.h"
0029
0030 /* core_44xx_pwrdm: CORE power domain */
0031 static struct powerdomain core_44xx_pwrdm = {
0032     .name         = "core_pwrdm",
0033     .voltdm       = { .name = "core" },
0034     .prcm_offs    = OMAP4430_PRM_CORE_INST,
0035     .prcm_partition   = OMAP4430_PRM_PARTITION,
0036     .pwrsts       = PWRSTS_RET_ON,
0037     .pwrsts_logic_ret = PWRSTS_OFF_RET,
0038     .banks        = 5,
0039     .pwrsts_mem_ret = {
0040         [0] = PWRSTS_OFF,   /* core_nret_bank */
0041         [1] = PWRSTS_RET,   /* core_ocmram */
0042         [2] = PWRSTS_RET,   /* core_other_bank */
0043         [3] = PWRSTS_OFF_RET,   /* ducati_l2ram */
0044         [4] = PWRSTS_OFF_RET,   /* ducati_unicache */
0045     },
0046     .pwrsts_mem_on  = {
0047         [0] = PWRSTS_ON,    /* core_nret_bank */
0048         [1] = PWRSTS_ON,    /* core_ocmram */
0049         [2] = PWRSTS_ON,    /* core_other_bank */
0050         [3] = PWRSTS_ON,    /* ducati_l2ram */
0051         [4] = PWRSTS_ON,    /* ducati_unicache */
0052     },
0053     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0054 };
0055
0056 /* gfx_44xx_pwrdm: 3D accelerator power domain */
0057 static struct powerdomain gfx_44xx_pwrdm = {
0058     .name         = "gfx_pwrdm",
0059     .voltdm       = { .name = "core" },
0060     .prcm_offs    = OMAP4430_PRM_GFX_INST,
0061     .prcm_partition   = OMAP4430_PRM_PARTITION,
0062     .pwrsts       = PWRSTS_OFF_ON,
0063     .banks        = 1,
0064     .pwrsts_mem_ret = {
0065         [0] = PWRSTS_OFF,   /* gfx_mem */
0066     },
0067     .pwrsts_mem_on  = {
0068         [0] = PWRSTS_ON,    /* gfx_mem */
0069     },
0070     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0071 };
0072
0073 /* abe_44xx_pwrdm: Audio back end power domain */
0074 static struct powerdomain abe_44xx_pwrdm = {
0075     .name         = "abe_pwrdm",
0076     .voltdm       = { .name = "iva" },
0077     .prcm_offs    = OMAP4430_PRM_ABE_INST,
0078     .prcm_partition   = OMAP4430_PRM_PARTITION,
0079     .pwrsts       = PWRSTS_OFF_RET_ON,
0080     .pwrsts_logic_ret = PWRSTS_OFF,
0081     .banks        = 2,
0082     .pwrsts_mem_ret = {
0083         [0] = PWRSTS_RET,   /* aessmem */
0084         [1] = PWRSTS_OFF,   /* periphmem */
0085     },
0086     .pwrsts_mem_on  = {
0087         [0] = PWRSTS_ON,    /* aessmem */
0088         [1] = PWRSTS_ON,    /* periphmem */
0089     },
0090     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0091 };
0092
0093 /* dss_44xx_pwrdm: Display subsystem power domain */
0094 static struct powerdomain dss_44xx_pwrdm = {
0095     .name         = "dss_pwrdm",
0096     .voltdm       = { .name = "core" },
0097     .prcm_offs    = OMAP4430_PRM_DSS_INST,
0098     .prcm_partition   = OMAP4430_PRM_PARTITION,
0099     .pwrsts       = PWRSTS_OFF_RET_ON,
0100     .pwrsts_logic_ret = PWRSTS_OFF,
0101     .banks        = 1,
0102     .pwrsts_mem_ret = {
0103         [0] = PWRSTS_OFF,   /* dss_mem */
0104     },
0105     .pwrsts_mem_on  = {
0106         [0] = PWRSTS_ON,    /* dss_mem */
0107     },
0108     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0109 };
0110
0111 /* tesla_44xx_pwrdm: Tesla processor power domain */
0112 static struct powerdomain tesla_44xx_pwrdm = {
0113     .name         = "tesla_pwrdm",
0114     .voltdm       = { .name = "iva" },
0115     .prcm_offs    = OMAP4430_PRM_TESLA_INST,
0116     .prcm_partition   = OMAP4430_PRM_PARTITION,
0117     .pwrsts       = PWRSTS_OFF_RET_ON,
0118     .pwrsts_logic_ret = PWRSTS_OFF_RET,
0119     .banks        = 3,
0120     .pwrsts_mem_ret = {
0121         [0] = PWRSTS_RET,   /* tesla_edma */
0122         [1] = PWRSTS_OFF_RET,   /* tesla_l1 */
0123         [2] = PWRSTS_OFF_RET,   /* tesla_l2 */
0124     },
0125     .pwrsts_mem_on  = {
0126         [0] = PWRSTS_ON,    /* tesla_edma */
0127         [1] = PWRSTS_ON,    /* tesla_l1 */
0128         [2] = PWRSTS_ON,    /* tesla_l2 */
0129     },
0130     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0131 };
0132
0133 /* wkup_44xx_pwrdm: Wake-up power domain */
0134 static struct powerdomain wkup_44xx_pwrdm = {
0135     .name         = "wkup_pwrdm",
0136     .voltdm       = { .name = "wakeup" },
0137     .prcm_offs    = OMAP4430_PRM_WKUP_INST,
0138     .prcm_partition   = OMAP4430_PRM_PARTITION,
0139     .pwrsts       = PWRSTS_ON,
0140     .banks        = 1,
0141     .pwrsts_mem_ret = {
0142         [0] = PWRSTS_OFF,   /* wkup_bank */
0143     },
0144     .pwrsts_mem_on  = {
0145         [0] = PWRSTS_ON,    /* wkup_bank */
0146     },
0147 };
0148
0149 /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
0150 static struct powerdomain cpu0_44xx_pwrdm = {
0151     .name         = "cpu0_pwrdm",
0152     .voltdm       = { .name = "mpu" },
0153     .prcm_offs    = OMAP4430_PRCM_MPU_CPU0_INST,
0154     .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
0155     .pwrsts       = PWRSTS_OFF_RET_ON,
0156     .pwrsts_logic_ret = PWRSTS_OFF_RET,
0157     .banks        = 1,
0158     .pwrsts_mem_ret = {
0159         [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
0160     },
0161     .pwrsts_mem_on  = {
0162         [0] = PWRSTS_ON,    /* cpu0_l1 */
0163     },
0164 };
0165
0166 /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
0167 static struct powerdomain cpu1_44xx_pwrdm = {
0168     .name         = "cpu1_pwrdm",
0169     .voltdm       = { .name = "mpu" },
0170     .prcm_offs    = OMAP4430_PRCM_MPU_CPU1_INST,
0171     .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
0172     .pwrsts       = PWRSTS_OFF_RET_ON,
0173     .pwrsts_logic_ret = PWRSTS_OFF_RET,
0174     .banks        = 1,
0175     .pwrsts_mem_ret = {
0176         [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
0177     },
0178     .pwrsts_mem_on  = {
0179         [0] = PWRSTS_ON,    /* cpu1_l1 */
0180     },
0181 };
0182
0183 /* emu_44xx_pwrdm: Emulation power domain */
0184 static struct powerdomain emu_44xx_pwrdm = {
0185     .name         = "emu_pwrdm",
0186     .voltdm       = { .name = "wakeup" },
0187     .prcm_offs    = OMAP4430_PRM_EMU_INST,
0188     .prcm_partition   = OMAP4430_PRM_PARTITION,
0189     .pwrsts       = PWRSTS_OFF_ON,
0190     .banks        = 1,
0191     .pwrsts_mem_ret = {
0192         [0] = PWRSTS_OFF,   /* emu_bank */
0193     },
0194     .pwrsts_mem_on  = {
0195         [0] = PWRSTS_ON,    /* emu_bank */
0196     },
0197 };
0198
0199 /* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
0200 static struct powerdomain mpu_44xx_pwrdm = {
0201     .name         = "mpu_pwrdm",
0202     .voltdm       = { .name = "mpu" },
0203     .prcm_offs    = OMAP4430_PRM_MPU_INST,
0204     .prcm_partition   = OMAP4430_PRM_PARTITION,
0205     .pwrsts       = PWRSTS_RET_ON,
0206     .pwrsts_logic_ret = PWRSTS_OFF_RET,
0207     .banks        = 3,
0208     .pwrsts_mem_ret = {
0209         [0] = PWRSTS_OFF_RET,   /* mpu_l1 */
0210         [1] = PWRSTS_OFF_RET,   /* mpu_l2 */
0211         [2] = PWRSTS_RET,   /* mpu_ram */
0212     },
0213     .pwrsts_mem_on  = {
0214         [0] = PWRSTS_ON,    /* mpu_l1 */
0215         [1] = PWRSTS_ON,    /* mpu_l2 */
0216         [2] = PWRSTS_ON,    /* mpu_ram */
0217     },
0218 };
0219
0220 /* ivahd_44xx_pwrdm: IVA-HD power domain */
0221 static struct powerdomain ivahd_44xx_pwrdm = {
0222     .name         = "ivahd_pwrdm",
0223     .voltdm       = { .name = "iva" },
0224     .prcm_offs    = OMAP4430_PRM_IVAHD_INST,
0225     .prcm_partition   = OMAP4430_PRM_PARTITION,
0226     .pwrsts       = PWRSTS_OFF_RET_ON,
0227     .pwrsts_logic_ret = PWRSTS_OFF,
0228     .banks        = 4,
0229     .pwrsts_mem_ret = {
0230         [0] = PWRSTS_OFF,   /* hwa_mem */
0231         [1] = PWRSTS_OFF_RET,   /* sl2_mem */
0232         [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
0233         [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
0234     },
0235     .pwrsts_mem_on  = {
0236         [0] = PWRSTS_ON,    /* hwa_mem */
0237         [1] = PWRSTS_ON,    /* sl2_mem */
0238         [2] = PWRSTS_ON,    /* tcm1_mem */
0239         [3] = PWRSTS_ON,    /* tcm2_mem */
0240     },
0241     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0242 };
0243
0244 /* cam_44xx_pwrdm: Camera subsystem power domain */
0245 static struct powerdomain cam_44xx_pwrdm = {
0246     .name         = "cam_pwrdm",
0247     .voltdm       = { .name = "core" },
0248     .prcm_offs    = OMAP4430_PRM_CAM_INST,
0249     .prcm_partition   = OMAP4430_PRM_PARTITION,
0250     .pwrsts       = PWRSTS_OFF_ON,
0251     .banks        = 1,
0252     .pwrsts_mem_ret = {
0253         [0] = PWRSTS_OFF,   /* cam_mem */
0254     },
0255     .pwrsts_mem_on  = {
0256         [0] = PWRSTS_ON,    /* cam_mem */
0257     },
0258     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0259 };
0260
0261 /* l3init_44xx_pwrdm: L3 initators pheripherals power domain  */
0262 static struct powerdomain l3init_44xx_pwrdm = {
0263     .name         = "l3init_pwrdm",
0264     .voltdm       = { .name = "core" },
0265     .prcm_offs    = OMAP4430_PRM_L3INIT_INST,
0266     .prcm_partition   = OMAP4430_PRM_PARTITION,
0267     .pwrsts       = PWRSTS_RET_ON,
0268     .pwrsts_logic_ret = PWRSTS_OFF_RET,
0269     .banks        = 1,
0270     .pwrsts_mem_ret = {
0271         [0] = PWRSTS_OFF,   /* l3init_bank1 */
0272     },
0273     .pwrsts_mem_on  = {
0274         [0] = PWRSTS_ON,    /* l3init_bank1 */
0275     },
0276     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0277 };
0278
0279 /* l4per_44xx_pwrdm: Target peripherals power domain */
0280 static struct powerdomain l4per_44xx_pwrdm = {
0281     .name         = "l4per_pwrdm",
0282     .voltdm       = { .name = "core" },
0283     .prcm_offs    = OMAP4430_PRM_L4PER_INST,
0284     .prcm_partition   = OMAP4430_PRM_PARTITION,
0285     .pwrsts       = PWRSTS_RET_ON,
0286     .pwrsts_logic_ret = PWRSTS_OFF_RET,
0287     .banks        = 2,
0288     .pwrsts_mem_ret = {
0289         [0] = PWRSTS_OFF,   /* nonretained_bank */
0290         [1] = PWRSTS_RET,   /* retained_bank */
0291     },
0292     .pwrsts_mem_on  = {
0293         [0] = PWRSTS_ON,    /* nonretained_bank */
0294         [1] = PWRSTS_ON,    /* retained_bank */
0295     },
0296     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0297 };
0298
0299 /*
0300  * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage
0301  * domain
0302  */
0303 static struct powerdomain always_on_core_44xx_pwrdm = {
0304     .name         = "always_on_core_pwrdm",
0305     .voltdm       = { .name = "core" },
0306     .prcm_offs    = OMAP4430_PRM_ALWAYS_ON_INST,
0307     .prcm_partition   = OMAP4430_PRM_PARTITION,
0308     .pwrsts       = PWRSTS_ON,
0309 };
0310
0311 /* cefuse_44xx_pwrdm: Customer efuse controller power domain */
0312 static struct powerdomain cefuse_44xx_pwrdm = {
0313     .name         = "cefuse_pwrdm",
0314     .voltdm       = { .name = "core" },
0315     .prcm_offs    = OMAP4430_PRM_CEFUSE_INST,
0316     .prcm_partition   = OMAP4430_PRM_PARTITION,
0317     .pwrsts       = PWRSTS_OFF_ON,
0318     .flags        = PWRDM_HAS_LOWPOWERSTATECHANGE,
0319 };
0320
0321 /*
0322  * The following power domains are not under SW control
0323  *
0324  * always_on_iva
0325  * always_on_mpu
0326  * stdefuse
0327  */
0328
0329 /* As powerdomains are added or removed above, this list must also be changed */
0330 static struct powerdomain *powerdomains_omap44xx[] __initdata = {
0331     &core_44xx_pwrdm,
0332     &gfx_44xx_pwrdm,
0333     &abe_44xx_pwrdm,
0334     &dss_44xx_pwrdm,
0335     &tesla_44xx_pwrdm,
0336     &wkup_44xx_pwrdm,
0337     &cpu0_44xx_pwrdm,
0338     &cpu1_44xx_pwrdm,
0339     &emu_44xx_pwrdm,
0340     &mpu_44xx_pwrdm,
0341     &ivahd_44xx_pwrdm,
0342     &cam_44xx_pwrdm,
0343     &l3init_44xx_pwrdm,
0344     &l4per_44xx_pwrdm,
0345     &always_on_core_44xx_pwrdm,
0346     &cefuse_44xx_pwrdm,
0347     NULL
0348 };
0349
0350 void __init omap44xx_powerdomains_init(void)
0351 {
0352     pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
0353     pwrdm_register_pwrdms(powerdomains_omap44xx);
0354     pwrdm_complete_init();
0355 }