arm/mach-omap2/powerdomains33xx_data.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * AM33XX Power domain data
0004  *
0005  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
0006  */
0007
0008 #include <linux/kernel.h>
0009 #include <linux/init.h>
0010
0011 #include "powerdomain.h"
0012 #include "prcm-common.h"
0013 #include "prm-regbits-33xx.h"
0014 #include "prm33xx.h"
0015
0016 static struct powerdomain gfx_33xx_pwrdm = {
0017     .name           = "gfx_pwrdm",
0018     .voltdm         = { .name = "core" },
0019     .prcm_offs      = AM33XX_PRM_GFX_MOD,
0020     .pwrstctrl_offs     = AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
0021     .pwrstst_offs       = AM33XX_PM_GFX_PWRSTST_OFFSET,
0022     .pwrsts         = PWRSTS_OFF_RET_ON,
0023     .pwrsts_logic_ret   = PWRSTS_OFF_RET,
0024     .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
0025     .banks          = 1,
0026     .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
0027     .mem_on_mask        = {
0028         [0]     = AM33XX_GFX_MEM_ONSTATE_MASK,  /* gfx_mem */
0029     },
0030     .mem_ret_mask       = {
0031         [0]     = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
0032     },
0033     .mem_pwrst_mask     = {
0034         [0]     = AM33XX_GFX_MEM_STATEST_MASK,  /* gfx_mem */
0035     },
0036     .mem_retst_mask     = {
0037         [0]     = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
0038     },
0039     .pwrsts_mem_ret     = {
0040         [0]     = PWRSTS_OFF_RET,   /* gfx_mem */
0041     },
0042     .pwrsts_mem_on      = {
0043         [0]     = PWRSTS_ON,        /* gfx_mem */
0044     },
0045 };
0046
0047 static struct powerdomain rtc_33xx_pwrdm = {
0048     .name           = "rtc_pwrdm",
0049     .voltdm         = { .name = "rtc" },
0050     .prcm_offs      = AM33XX_PRM_RTC_MOD,
0051     .pwrstctrl_offs     = AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
0052     .pwrstst_offs       = AM33XX_PM_RTC_PWRSTST_OFFSET,
0053     .pwrsts         = PWRSTS_ON,
0054     .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
0055 };
0056
0057 static struct powerdomain wkup_33xx_pwrdm = {
0058     .name           = "wkup_pwrdm",
0059     .voltdm         = { .name = "core" },
0060     .prcm_offs      = AM33XX_PRM_WKUP_MOD,
0061     .pwrstctrl_offs     = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
0062     .pwrstst_offs       = AM33XX_PM_WKUP_PWRSTST_OFFSET,
0063     .pwrsts         = PWRSTS_ON,
0064     .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
0065 };
0066
0067 static struct powerdomain per_33xx_pwrdm = {
0068     .name           = "per_pwrdm",
0069     .voltdm         = { .name = "core" },
0070     .prcm_offs      = AM33XX_PRM_PER_MOD,
0071     .pwrstctrl_offs     = AM33XX_PM_PER_PWRSTCTRL_OFFSET,
0072     .pwrstst_offs       = AM33XX_PM_PER_PWRSTST_OFFSET,
0073     .pwrsts         = PWRSTS_OFF_RET_ON,
0074     .pwrsts_logic_ret   = PWRSTS_OFF_RET,
0075     .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
0076     .banks          = 3,
0077     .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
0078     .mem_on_mask        = {
0079         [0]     = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */
0080         [1]     = AM33XX_PER_MEM_ONSTATE_MASK,  /* per_mem */
0081         [2]     = AM33XX_RAM_MEM_ONSTATE_MASK,  /* ram_mem */
0082     },
0083     .mem_ret_mask       = {
0084         [0]     = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
0085         [1]     = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
0086         [2]     = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
0087     },
0088     .mem_pwrst_mask     = {
0089         [0]     = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */
0090         [1]     = AM33XX_PER_MEM_STATEST_MASK,  /* per_mem */
0091         [2]     = AM33XX_RAM_MEM_STATEST_MASK,  /* ram_mem */
0092     },
0093     .mem_retst_mask     = {
0094         [0]     = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
0095         [1]     = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
0096         [2]     = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
0097     },
0098     .pwrsts_mem_ret     = {
0099         [0]     = PWRSTS_OFF_RET,   /* pruss_mem */
0100         [1]     = PWRSTS_OFF_RET,   /* per_mem */
0101         [2]     = PWRSTS_OFF_RET,   /* ram_mem */
0102     },
0103     .pwrsts_mem_on      = {
0104         [0]     = PWRSTS_ON,        /* pruss_mem */
0105         [1]     = PWRSTS_ON,        /* per_mem */
0106         [2]     = PWRSTS_ON,        /* ram_mem */
0107     },
0108 };
0109
0110 static struct powerdomain mpu_33xx_pwrdm = {
0111     .name           = "mpu_pwrdm",
0112     .voltdm         = { .name = "mpu" },
0113     .prcm_offs      = AM33XX_PRM_MPU_MOD,
0114     .pwrstctrl_offs     = AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
0115     .pwrstst_offs       = AM33XX_PM_MPU_PWRSTST_OFFSET,
0116     .pwrsts         = PWRSTS_OFF_RET_ON,
0117     .pwrsts_logic_ret   = PWRSTS_OFF_RET,
0118     .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
0119     .banks          = 3,
0120     .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
0121     .mem_on_mask        = {
0122         [0]     = AM33XX_MPU_L1_ONSTATE_MASK,   /* mpu_l1 */
0123         [1]     = AM33XX_MPU_L2_ONSTATE_MASK,   /* mpu_l2 */
0124         [2]     = AM33XX_MPU_RAM_ONSTATE_MASK,  /* mpu_ram */
0125     },
0126     .mem_ret_mask       = {
0127         [0]     = AM33XX_MPU_L1_RETSTATE_MASK,  /* mpu_l1 */
0128         [1]     = AM33XX_MPU_L2_RETSTATE_MASK,  /* mpu_l2 */
0129         [2]     = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
0130     },
0131     .mem_pwrst_mask     = {
0132         [0]     = AM33XX_MPU_L1_STATEST_MASK,   /* mpu_l1 */
0133         [1]     = AM33XX_MPU_L2_STATEST_MASK,   /* mpu_l2 */
0134         [2]     = AM33XX_MPU_RAM_STATEST_MASK,  /* mpu_ram */
0135     },
0136     .mem_retst_mask     = {
0137         [0]     = AM33XX_MPU_L1_RETSTATE_MASK,  /* mpu_l1 */
0138         [1]     = AM33XX_MPU_L2_RETSTATE_MASK,  /* mpu_l2 */
0139         [2]     = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
0140     },
0141     .pwrsts_mem_ret     = {
0142         [0]     = PWRSTS_OFF_RET,   /* mpu_l1 */
0143         [1]     = PWRSTS_OFF_RET,   /* mpu_l2 */
0144         [2]     = PWRSTS_OFF_RET,   /* mpu_ram */
0145     },
0146     .pwrsts_mem_on      = {
0147         [0]     = PWRSTS_ON,        /* mpu_l1 */
0148         [1]     = PWRSTS_ON,        /* mpu_l2 */
0149         [2]     = PWRSTS_ON,        /* mpu_ram */
0150     },
0151 };
0152
0153 static struct powerdomain cefuse_33xx_pwrdm = {
0154     .name       = "cefuse_pwrdm",
0155     .voltdm     = { .name = "core" },
0156     .prcm_offs  = AM33XX_PRM_CEFUSE_MOD,
0157     .pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
0158     .pwrstst_offs   = AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
0159     .pwrsts     = PWRSTS_OFF_ON,
0160 };
0161
0162 static struct powerdomain *powerdomains_am33xx[] __initdata = {
0163     &gfx_33xx_pwrdm,
0164     &rtc_33xx_pwrdm,
0165     &wkup_33xx_pwrdm,
0166     &per_33xx_pwrdm,
0167     &mpu_33xx_pwrdm,
0168     &cefuse_33xx_pwrdm,
0169     NULL,
0170 };
0171
0172 void __init am33xx_powerdomains_init(void)
0173 {
0174     pwrdm_register_platform_funcs(&am33xx_pwrdm_operations);
0175     pwrdm_register_pwrdms(powerdomains_am33xx);
0176     pwrdm_complete_init();
0177 }