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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * OMAP3 Power Management Routines
0004  *
0005  * Copyright (C) 2006-2008 Nokia Corporation
0006  * Tony Lindgren <tony@atomide.com>
0007  * Jouni Hogander
0008  *
0009  * Copyright (C) 2007 Texas Instruments, Inc.
0010  * Rajendra Nayak <rnayak@ti.com>
0011  *
0012  * Copyright (C) 2005 Texas Instruments, Inc.
0013  * Richard Woodruff <r-woodruff2@ti.com>
0014  *
0015  * Based on pm.c for omap1
0016  */
0017 
0018 #include <linux/cpu_pm.h>
0019 #include <linux/pm.h>
0020 #include <linux/suspend.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/module.h>
0023 #include <linux/list.h>
0024 #include <linux/err.h>
0025 #include <linux/clk.h>
0026 #include <linux/delay.h>
0027 #include <linux/slab.h>
0028 #include <linux/of.h>
0029 
0030 #include <trace/events/power.h>
0031 
0032 #include <asm/fncpy.h>
0033 #include <asm/suspend.h>
0034 #include <asm/system_misc.h>
0035 
0036 #include "clockdomain.h"
0037 #include "powerdomain.h"
0038 #include "soc.h"
0039 #include "common.h"
0040 #include "cm3xxx.h"
0041 #include "cm-regbits-34xx.h"
0042 #include "prm-regbits-34xx.h"
0043 #include "prm3xxx.h"
0044 #include "pm.h"
0045 #include "sdrc.h"
0046 #include "omap-secure.h"
0047 #include "sram.h"
0048 #include "control.h"
0049 #include "vc.h"
0050 
0051 /* pm34xx errata defined in pm.h */
0052 u16 pm34xx_errata;
0053 
0054 struct power_state {
0055     struct powerdomain *pwrdm;
0056     u32 next_state;
0057 #ifdef CONFIG_SUSPEND
0058     u32 saved_state;
0059 #endif
0060     struct list_head node;
0061 };
0062 
0063 static LIST_HEAD(pwrst_list);
0064 
0065 void (*omap3_do_wfi_sram)(void);
0066 
0067 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
0068 static struct powerdomain *core_pwrdm, *per_pwrdm;
0069 
0070 static void omap3_core_save_context(void)
0071 {
0072     omap3_ctrl_save_padconf();
0073 
0074     /*
0075      * Force write last pad into memory, as this can fail in some
0076      * cases according to errata 1.157, 1.185
0077      */
0078     omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
0079         OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
0080 
0081     /* Save the Interrupt controller context */
0082     omap_intc_save_context();
0083     /* Save the system control module context, padconf already save above*/
0084     omap3_control_save_context();
0085 }
0086 
0087 static void omap3_core_restore_context(void)
0088 {
0089     /* Restore the control module context, padconf restored by h/w */
0090     omap3_control_restore_context();
0091     /* Restore the interrupt controller context */
0092     omap_intc_restore_context();
0093 }
0094 
0095 /*
0096  * FIXME: This function should be called before entering off-mode after
0097  * OMAP3 secure services have been accessed. Currently it is only called
0098  * once during boot sequence, but this works as we are not using secure
0099  * services.
0100  */
0101 static void omap3_save_secure_ram_context(void)
0102 {
0103     u32 ret;
0104     int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
0105 
0106     if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
0107         /*
0108          * MPU next state must be set to POWER_ON temporarily,
0109          * otherwise the WFI executed inside the ROM code
0110          * will hang the system.
0111          */
0112         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
0113         ret = omap3_save_secure_ram(omap3_secure_ram_storage,
0114                         OMAP3_SAVE_SECURE_RAM_SZ);
0115         pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
0116         /* Following is for error tracking, it should not happen */
0117         if (ret) {
0118             pr_err("save_secure_sram() returns %08x\n", ret);
0119             while (1)
0120                 ;
0121         }
0122     }
0123 }
0124 
0125 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
0126 {
0127     int c;
0128 
0129     c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
0130                     OMAP3430_ST_IO_CHAIN_MASK);
0131 
0132     return c ? IRQ_HANDLED : IRQ_NONE;
0133 }
0134 
0135 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
0136 {
0137     int c;
0138 
0139     /*
0140      * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
0141      * these are handled in a separate handler to avoid acking
0142      * IO events before parsing in mux code
0143      */
0144     c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
0145                            OMAP3430_ST_IO_CHAIN_MASK));
0146     c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
0147     c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
0148     if (omap_rev() > OMAP3430_REV_ES1_0) {
0149         c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
0150         c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
0151     }
0152 
0153     return c ? IRQ_HANDLED : IRQ_NONE;
0154 }
0155 
0156 static void omap34xx_save_context(u32 *save)
0157 {
0158     u32 val;
0159 
0160     /* Read Auxiliary Control Register */
0161     asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
0162     *save++ = 1;
0163     *save++ = val;
0164 
0165     /* Read L2 AUX ctrl register */
0166     asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
0167     *save++ = 1;
0168     *save++ = val;
0169 }
0170 
0171 static int omap34xx_do_sram_idle(unsigned long save_state)
0172 {
0173     omap34xx_cpu_suspend(save_state);
0174     return 0;
0175 }
0176 
0177 void omap_sram_idle(void)
0178 {
0179     /* Variable to tell what needs to be saved and restored
0180      * in omap_sram_idle*/
0181     /* save_state = 0 => Nothing to save and restored */
0182     /* save_state = 1 => Only L1 and logic lost */
0183     /* save_state = 2 => Only L2 lost */
0184     /* save_state = 3 => L1, L2 and logic lost */
0185     int save_state = 0;
0186     int mpu_next_state = PWRDM_POWER_ON;
0187     int per_next_state = PWRDM_POWER_ON;
0188     int core_next_state = PWRDM_POWER_ON;
0189     u32 sdrc_pwr = 0;
0190     int error;
0191 
0192     mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
0193     switch (mpu_next_state) {
0194     case PWRDM_POWER_ON:
0195     case PWRDM_POWER_RET:
0196         /* No need to save context */
0197         save_state = 0;
0198         break;
0199     case PWRDM_POWER_OFF:
0200         save_state = 3;
0201         break;
0202     default:
0203         /* Invalid state */
0204         pr_err("Invalid mpu state in sram_idle\n");
0205         return;
0206     }
0207 
0208     /* NEON control */
0209     if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
0210         pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
0211 
0212     /* Enable IO-PAD and IO-CHAIN wakeups */
0213     per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
0214     core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
0215 
0216     pwrdm_pre_transition(NULL);
0217 
0218     /* PER */
0219     if (per_next_state == PWRDM_POWER_OFF) {
0220         error = cpu_cluster_pm_enter();
0221         if (error)
0222             return;
0223     }
0224 
0225     /* CORE */
0226     if (core_next_state < PWRDM_POWER_ON) {
0227         if (core_next_state == PWRDM_POWER_OFF) {
0228             omap3_core_save_context();
0229             omap3_cm_save_context();
0230         }
0231     }
0232 
0233     /* Configure PMIC signaling for I2C4 or sys_off_mode */
0234     omap3_vc_set_pmic_signaling(core_next_state);
0235 
0236     omap3_intc_prepare_idle();
0237 
0238     /*
0239      * On EMU/HS devices ROM code restores a SRDC value
0240      * from scratchpad which has automatic self refresh on timeout
0241      * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
0242      * Hence store/restore the SDRC_POWER register here.
0243      */
0244     if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
0245         (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
0246          omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
0247         core_next_state == PWRDM_POWER_OFF)
0248         sdrc_pwr = sdrc_read_reg(SDRC_POWER);
0249 
0250     /*
0251      * omap3_arm_context is the location where some ARM context
0252      * get saved. The rest is placed on the stack, and restored
0253      * from there before resuming.
0254      */
0255     if (save_state)
0256         omap34xx_save_context(omap3_arm_context);
0257     if (save_state == 1 || save_state == 3)
0258         cpu_suspend(save_state, omap34xx_do_sram_idle);
0259     else
0260         omap34xx_do_sram_idle(save_state);
0261 
0262     /* Restore normal SDRC POWER settings */
0263     if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
0264         (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
0265          omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
0266         core_next_state == PWRDM_POWER_OFF)
0267         sdrc_write_reg(sdrc_pwr, SDRC_POWER);
0268 
0269     /* CORE */
0270     if (core_next_state < PWRDM_POWER_ON &&
0271         pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
0272         omap3_core_restore_context();
0273         omap3_cm_restore_context();
0274         omap3_sram_restore_context();
0275         omap2_sms_restore_context();
0276     } else {
0277         /*
0278          * In off-mode resume path above, omap3_core_restore_context
0279          * also handles the INTC autoidle restore done here so limit
0280          * this to non-off mode resume paths so we don't do it twice.
0281          */
0282         omap3_intc_resume_idle();
0283     }
0284 
0285     pwrdm_post_transition(NULL);
0286 
0287     /* PER */
0288     if (per_next_state == PWRDM_POWER_OFF)
0289         cpu_cluster_pm_exit();
0290 }
0291 
0292 static void omap3_pm_idle(void)
0293 {
0294     if (omap_irq_pending())
0295         return;
0296 
0297     omap_sram_idle();
0298 }
0299 
0300 #ifdef CONFIG_SUSPEND
0301 static int omap3_pm_suspend(void)
0302 {
0303     struct power_state *pwrst;
0304     int state, ret = 0;
0305 
0306     /* Read current next_pwrsts */
0307     list_for_each_entry(pwrst, &pwrst_list, node)
0308         pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
0309     /* Set ones wanted by suspend */
0310     list_for_each_entry(pwrst, &pwrst_list, node) {
0311         if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
0312             goto restore;
0313         if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
0314             goto restore;
0315     }
0316 
0317     omap3_intc_suspend();
0318 
0319     omap_sram_idle();
0320 
0321 restore:
0322     /* Restore next_pwrsts */
0323     list_for_each_entry(pwrst, &pwrst_list, node) {
0324         state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
0325         if (state > pwrst->next_state) {
0326             pr_info("Powerdomain (%s) didn't enter target state %d\n",
0327                 pwrst->pwrdm->name, pwrst->next_state);
0328             ret = -1;
0329         }
0330         omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
0331     }
0332     if (ret)
0333         pr_err("Could not enter target state in pm_suspend\n");
0334     else
0335         pr_info("Successfully put all powerdomains to target state\n");
0336 
0337     return ret;
0338 }
0339 #else
0340 #define omap3_pm_suspend NULL
0341 #endif /* CONFIG_SUSPEND */
0342 
0343 static void __init prcm_setup_regs(void)
0344 {
0345     omap3_ctrl_init();
0346 
0347     omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
0348 }
0349 
0350 void omap3_pm_off_mode_enable(int enable)
0351 {
0352     struct power_state *pwrst;
0353     u32 state;
0354 
0355     if (enable)
0356         state = PWRDM_POWER_OFF;
0357     else
0358         state = PWRDM_POWER_RET;
0359 
0360     list_for_each_entry(pwrst, &pwrst_list, node) {
0361         if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
0362                 pwrst->pwrdm == core_pwrdm &&
0363                 state == PWRDM_POWER_OFF) {
0364             pwrst->next_state = PWRDM_POWER_RET;
0365             pr_warn("%s: Core OFF disabled due to errata i583\n",
0366                 __func__);
0367         } else {
0368             pwrst->next_state = state;
0369         }
0370         omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
0371     }
0372 }
0373 
0374 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
0375 {
0376     struct power_state *pwrst;
0377 
0378     list_for_each_entry(pwrst, &pwrst_list, node) {
0379         if (pwrst->pwrdm == pwrdm)
0380             return pwrst->next_state;
0381     }
0382     return -EINVAL;
0383 }
0384 
0385 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
0386 {
0387     struct power_state *pwrst;
0388 
0389     list_for_each_entry(pwrst, &pwrst_list, node) {
0390         if (pwrst->pwrdm == pwrdm) {
0391             pwrst->next_state = state;
0392             return 0;
0393         }
0394     }
0395     return -EINVAL;
0396 }
0397 
0398 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
0399 {
0400     struct power_state *pwrst;
0401 
0402     if (!pwrdm->pwrsts)
0403         return 0;
0404 
0405     pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
0406     if (!pwrst)
0407         return -ENOMEM;
0408     pwrst->pwrdm = pwrdm;
0409 
0410     if (enable_off_mode)
0411         pwrst->next_state = PWRDM_POWER_OFF;
0412     else
0413         pwrst->next_state = PWRDM_POWER_RET;
0414 
0415     list_add(&pwrst->node, &pwrst_list);
0416 
0417     if (pwrdm_has_hdwr_sar(pwrdm))
0418         pwrdm_enable_hdwr_sar(pwrdm);
0419 
0420     return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
0421 }
0422 
0423 /*
0424  * Push functions to SRAM
0425  *
0426  * The minimum set of functions is pushed to SRAM for execution:
0427  * - omap3_do_wfi for erratum i581 WA,
0428  */
0429 void omap_push_sram_idle(void)
0430 {
0431     omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
0432 }
0433 
0434 static void __init pm_errata_configure(void)
0435 {
0436     if (cpu_is_omap3630()) {
0437         pm34xx_errata |= PM_RTA_ERRATUM_i608;
0438         /* Enable the l2 cache toggling in sleep logic */
0439         enable_omap3630_toggle_l2_on_restore();
0440         if (omap_rev() < OMAP3630_REV_ES1_2)
0441             pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
0442                       PM_PER_MEMORIES_ERRATUM_i582);
0443     } else if (cpu_is_omap34xx()) {
0444         pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
0445     }
0446 }
0447 
0448 static void __init omap3_pm_check_pmic(void)
0449 {
0450     struct device_node *np;
0451 
0452     np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle");
0453     if (!np)
0454         np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle-osc-off");
0455 
0456     if (np) {
0457         of_node_put(np);
0458         enable_off_mode = 1;
0459     } else {
0460         enable_off_mode = 0;
0461     }
0462 }
0463 
0464 int __init omap3_pm_init(void)
0465 {
0466     struct power_state *pwrst, *tmp;
0467     struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
0468     int ret;
0469 
0470     if (!omap3_has_io_chain_ctrl())
0471         pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");
0472 
0473     pm_errata_configure();
0474 
0475     /* XXX prcm_setup_regs needs to be before enabling hw
0476      * supervised mode for powerdomains */
0477     prcm_setup_regs();
0478 
0479     ret = request_irq(omap_prcm_event_to_irq("wkup"),
0480         _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
0481 
0482     if (ret) {
0483         pr_err("pm: Failed to request pm_wkup irq\n");
0484         goto err1;
0485     }
0486 
0487     /* IO interrupt is shared with mux code */
0488     ret = request_irq(omap_prcm_event_to_irq("io"),
0489         _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
0490         omap3_pm_init);
0491 
0492     if (ret) {
0493         pr_err("pm: Failed to request pm_io irq\n");
0494         goto err2;
0495     }
0496 
0497     omap3_pm_check_pmic();
0498 
0499     ret = pwrdm_for_each(pwrdms_setup, NULL);
0500     if (ret) {
0501         pr_err("Failed to setup powerdomains\n");
0502         goto err3;
0503     }
0504 
0505     (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
0506 
0507     mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
0508     if (mpu_pwrdm == NULL) {
0509         pr_err("Failed to get mpu_pwrdm\n");
0510         ret = -EINVAL;
0511         goto err3;
0512     }
0513 
0514     neon_pwrdm = pwrdm_lookup("neon_pwrdm");
0515     per_pwrdm = pwrdm_lookup("per_pwrdm");
0516     core_pwrdm = pwrdm_lookup("core_pwrdm");
0517 
0518     neon_clkdm = clkdm_lookup("neon_clkdm");
0519     mpu_clkdm = clkdm_lookup("mpu_clkdm");
0520     per_clkdm = clkdm_lookup("per_clkdm");
0521     wkup_clkdm = clkdm_lookup("wkup_clkdm");
0522 
0523     omap_common_suspend_init(omap3_pm_suspend);
0524 
0525     arm_pm_idle = omap3_pm_idle;
0526     omap3_idle_init();
0527 
0528     /*
0529      * RTA is disabled during initialization as per erratum i608
0530      * it is safer to disable RTA by the bootloader, but we would like
0531      * to be doubly sure here and prevent any mishaps.
0532      */
0533     if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
0534         omap3630_ctrl_disable_rta();
0535 
0536     /*
0537      * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
0538      * not correctly reset when the PER powerdomain comes back
0539      * from OFF or OSWR when the CORE powerdomain is kept active.
0540      * See OMAP36xx Erratum i582 "PER Domain reset issue after
0541      * Domain-OFF/OSWR Wakeup".  This wakeup dependency is not a
0542      * complete workaround.  The kernel must also prevent the PER
0543      * powerdomain from going to OSWR/OFF while the CORE
0544      * powerdomain is not going to OSWR/OFF.  And if PER last
0545      * power state was off while CORE last power state was ON, the
0546      * UART3/4 and McBSP2/3 SIDETONE devices need to run a
0547      * self-test using their loopback tests; if that fails, those
0548      * devices are unusable until the PER/CORE can complete a transition
0549      * from ON to OSWR/OFF and then back to ON.
0550      *
0551      * XXX Technically this workaround is only needed if off-mode
0552      * or OSWR is enabled.
0553      */
0554     if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
0555         clkdm_add_wkdep(per_clkdm, wkup_clkdm);
0556 
0557     clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
0558     if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
0559         omap3_secure_ram_storage =
0560             kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL);
0561         if (!omap3_secure_ram_storage)
0562             pr_err("Memory allocation failed when allocating for secure sram context\n");
0563 
0564         local_irq_disable();
0565 
0566         omap3_save_secure_ram_context();
0567 
0568         local_irq_enable();
0569     }
0570 
0571     omap3_save_scratchpad_contents();
0572     return ret;
0573 
0574 err3:
0575     list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
0576         list_del(&pwrst->node);
0577         kfree(pwrst);
0578     }
0579     free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
0580 err2:
0581     free_irq(omap_prcm_event_to_irq("wkup"), NULL);
0582 err1:
0583     return ret;
0584 }
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