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0009 #include <linux/cpuidle.h>
0010 #include <linux/platform_data/pm33xx.h>
0011 #include <linux/suspend.h>
0012 #include <asm/cpuidle.h>
0013 #include <asm/smp_scu.h>
0014 #include <asm/suspend.h>
0015 #include <linux/errno.h>
0016 #include <linux/clk.h>
0017 #include <linux/cpu.h>
0018 #include <linux/platform_data/gpio-omap.h>
0019 #include <linux/pinctrl/pinmux.h>
0020 #include <linux/wkup_m3_ipc.h>
0021 #include <linux/of.h>
0022 #include <linux/rtc.h>
0023
0024 #include "cm33xx.h"
0025 #include "common.h"
0026 #include "control.h"
0027 #include "clockdomain.h"
0028 #include "iomap.h"
0029 #include "pm.h"
0030 #include "powerdomain.h"
0031 #include "prm33xx.h"
0032 #include "soc.h"
0033 #include "sram.h"
0034 #include "omap-secure.h"
0035
0036 static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm;
0037 static struct clockdomain *gfx_l4ls_clkdm;
0038 static void __iomem *scu_base;
0039
0040 static int (*idle_fn)(u32 wfi_flags);
0041
0042 struct amx3_idle_state {
0043 int wfi_flags;
0044 };
0045
0046 static struct amx3_idle_state *idle_states;
0047
0048 static int am43xx_map_scu(void)
0049 {
0050 scu_base = ioremap(scu_a9_get_base(), SZ_256);
0051
0052 if (!scu_base)
0053 return -ENOMEM;
0054
0055 return 0;
0056 }
0057
0058 static int am33xx_check_off_mode_enable(void)
0059 {
0060 if (enable_off_mode)
0061 pr_warn("WARNING: This platform does not support off-mode, entering DeepSleep suspend.\n");
0062
0063
0064 return 0;
0065 }
0066
0067 static int am43xx_check_off_mode_enable(void)
0068 {
0069
0070
0071
0072
0073 if (of_machine_is_compatible("ti,am437x-gp-evm") && enable_off_mode)
0074 return enable_off_mode;
0075 else if (enable_off_mode)
0076 pr_warn("WARNING: This platform does not support off-mode, entering DeepSleep suspend.\n");
0077
0078 return 0;
0079 }
0080
0081 static int amx3_common_init(int (*idle)(u32 wfi_flags))
0082 {
0083 gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
0084 per_pwrdm = pwrdm_lookup("per_pwrdm");
0085 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
0086
0087 if ((!gfx_pwrdm) || (!per_pwrdm) || (!mpu_pwrdm))
0088 return -ENODEV;
0089
0090 (void)clkdm_for_each(omap_pm_clkdms_setup, NULL);
0091
0092
0093 cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
0094 if (!cefuse_pwrdm)
0095 pr_err("PM: Failed to get cefuse_pwrdm\n");
0096 else if (omap_type() != OMAP2_DEVICE_TYPE_GP)
0097 pr_info("PM: Leaving EFUSE power domain active\n");
0098 else
0099 omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF);
0100
0101 idle_fn = idle;
0102
0103 return 0;
0104 }
0105
0106 static int am33xx_suspend_init(int (*idle)(u32 wfi_flags))
0107 {
0108 int ret;
0109
0110 gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
0111
0112 if (!gfx_l4ls_clkdm) {
0113 pr_err("PM: Cannot lookup gfx_l4ls_clkdm clockdomains\n");
0114 return -ENODEV;
0115 }
0116
0117 ret = amx3_common_init(idle);
0118
0119 return ret;
0120 }
0121
0122 static int am43xx_suspend_init(int (*idle)(u32 wfi_flags))
0123 {
0124 int ret = 0;
0125
0126 ret = am43xx_map_scu();
0127 if (ret) {
0128 pr_err("PM: Could not ioremap SCU\n");
0129 return ret;
0130 }
0131
0132 ret = amx3_common_init(idle);
0133
0134 return ret;
0135 }
0136
0137 static int amx3_suspend_deinit(void)
0138 {
0139 idle_fn = NULL;
0140 return 0;
0141 }
0142
0143 static void amx3_pre_suspend_common(void)
0144 {
0145 omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF);
0146 }
0147
0148 static void amx3_post_suspend_common(void)
0149 {
0150 int status;
0151
0152
0153
0154
0155 status = pwrdm_read_pwrst(gfx_pwrdm);
0156 if (status != PWRDM_POWER_OFF)
0157 pr_err("PM: GFX domain did not transition: %x\n", status);
0158 }
0159
0160 static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long),
0161 unsigned long args)
0162 {
0163 int ret = 0;
0164
0165 amx3_pre_suspend_common();
0166 ret = cpu_suspend(args, fn);
0167 amx3_post_suspend_common();
0168
0169
0170
0171
0172
0173
0174
0175
0176
0177 clkdm_wakeup(gfx_l4ls_clkdm);
0178 clkdm_sleep(gfx_l4ls_clkdm);
0179
0180 return ret;
0181 }
0182
0183 static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long),
0184 unsigned long args)
0185 {
0186 int ret = 0;
0187
0188
0189 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
0190 if (optee_available)
0191 omap_smccc_smc(AM43xx_PPA_SVC_PM_SUSPEND, 0);
0192 else
0193 omap_secure_dispatcher(AM43xx_PPA_SVC_PM_SUSPEND,
0194 FLAG_START_CRITICAL,
0195 0, 0, 0, 0, 0);
0196 }
0197
0198 amx3_pre_suspend_common();
0199 scu_power_mode(scu_base, SCU_PM_POWEROFF);
0200 ret = cpu_suspend(args, fn);
0201 scu_power_mode(scu_base, SCU_PM_NORMAL);
0202
0203 if (!am43xx_check_off_mode_enable())
0204 amx3_post_suspend_common();
0205
0206
0207
0208
0209
0210
0211
0212
0213
0214 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
0215 omap_secure_dispatcher(AM43xx_PPA_SVC_PM_RESUME,
0216 FLAG_START_CRITICAL,
0217 0, 0, 0, 0, 0);
0218
0219 return ret;
0220 }
0221
0222 static int am33xx_cpu_suspend(int (*fn)(unsigned long), unsigned long args)
0223 {
0224 int ret = 0;
0225
0226 if (omap_irq_pending() || need_resched())
0227 return ret;
0228
0229 ret = cpu_suspend(args, fn);
0230
0231 return ret;
0232 }
0233
0234 static int am43xx_cpu_suspend(int (*fn)(unsigned long), unsigned long args)
0235 {
0236 int ret = 0;
0237
0238 if (!scu_base)
0239 return 0;
0240
0241 scu_power_mode(scu_base, SCU_PM_DORMANT);
0242 ret = cpu_suspend(args, fn);
0243 scu_power_mode(scu_base, SCU_PM_NORMAL);
0244
0245 return ret;
0246 }
0247
0248 static void amx3_begin_suspend(void)
0249 {
0250 cpu_idle_poll_ctrl(true);
0251 }
0252
0253 static void amx3_finish_suspend(void)
0254 {
0255 cpu_idle_poll_ctrl(false);
0256 }
0257
0258
0259 static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void)
0260 {
0261 if (soc_is_am33xx())
0262 return &am33xx_pm_sram;
0263 else if (soc_is_am437x())
0264 return &am43xx_pm_sram;
0265 else
0266 return NULL;
0267 }
0268
0269 static void am43xx_save_context(void)
0270 {
0271 }
0272
0273 static void am33xx_save_context(void)
0274 {
0275 omap_intc_save_context();
0276 }
0277
0278 static void am33xx_restore_context(void)
0279 {
0280 omap_intc_restore_context();
0281 }
0282
0283 static void am43xx_restore_context(void)
0284 {
0285
0286
0287
0288
0289 writel_relaxed(0x0, AM33XX_L4_WK_IO_ADDRESS(0x44df2e14));
0290 }
0291
0292 static struct am33xx_pm_platform_data am33xx_ops = {
0293 .init = am33xx_suspend_init,
0294 .deinit = amx3_suspend_deinit,
0295 .soc_suspend = am33xx_suspend,
0296 .cpu_suspend = am33xx_cpu_suspend,
0297 .begin_suspend = amx3_begin_suspend,
0298 .finish_suspend = amx3_finish_suspend,
0299 .get_sram_addrs = amx3_get_sram_addrs,
0300 .save_context = am33xx_save_context,
0301 .restore_context = am33xx_restore_context,
0302 .check_off_mode_enable = am33xx_check_off_mode_enable,
0303 };
0304
0305 static struct am33xx_pm_platform_data am43xx_ops = {
0306 .init = am43xx_suspend_init,
0307 .deinit = amx3_suspend_deinit,
0308 .soc_suspend = am43xx_suspend,
0309 .cpu_suspend = am43xx_cpu_suspend,
0310 .begin_suspend = amx3_begin_suspend,
0311 .finish_suspend = amx3_finish_suspend,
0312 .get_sram_addrs = amx3_get_sram_addrs,
0313 .save_context = am43xx_save_context,
0314 .restore_context = am43xx_restore_context,
0315 .check_off_mode_enable = am43xx_check_off_mode_enable,
0316 };
0317
0318 static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void)
0319 {
0320 if (soc_is_am33xx())
0321 return &am33xx_ops;
0322 else if (soc_is_am437x())
0323 return &am43xx_ops;
0324 else
0325 return NULL;
0326 }
0327
0328 #ifdef CONFIG_SUSPEND
0329
0330
0331
0332
0333
0334 static int amx3_suspend_block(suspend_state_t state)
0335 {
0336 pr_warn("PM not initialized for pm33xx, wkup_m3_ipc, or am335x-pm-firmware.elf\n");
0337
0338 return -EINVAL;
0339 }
0340
0341 static int amx3_pm_valid(suspend_state_t state)
0342 {
0343 switch (state) {
0344 case PM_SUSPEND_STANDBY:
0345 return 1;
0346 default:
0347 return 0;
0348 }
0349 }
0350
0351 static const struct platform_suspend_ops amx3_blocked_pm_ops = {
0352 .begin = amx3_suspend_block,
0353 .valid = amx3_pm_valid,
0354 };
0355
0356 static void __init amx3_block_suspend(void)
0357 {
0358 suspend_set_ops(&amx3_blocked_pm_ops);
0359 }
0360 #else
0361 static inline void amx3_block_suspend(void)
0362 {
0363 }
0364 #endif
0365
0366 int __init amx3_common_pm_init(void)
0367 {
0368 struct am33xx_pm_platform_data *pdata;
0369 struct platform_device_info devinfo;
0370
0371 pdata = am33xx_pm_get_pdata();
0372
0373 memset(&devinfo, 0, sizeof(devinfo));
0374 devinfo.name = "pm33xx";
0375 devinfo.data = pdata;
0376 devinfo.size_data = sizeof(*pdata);
0377 devinfo.id = -1;
0378 platform_device_register_full(&devinfo);
0379 amx3_block_suspend();
0380
0381 return 0;
0382 }
0383
0384 static int __init amx3_idle_init(struct device_node *cpu_node, int cpu)
0385 {
0386 struct device_node *state_node;
0387 struct amx3_idle_state states[CPUIDLE_STATE_MAX];
0388 int i;
0389 int state_count = 1;
0390
0391 for (i = 0; ; i++) {
0392 state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
0393 if (!state_node)
0394 break;
0395
0396 if (!of_device_is_available(state_node))
0397 continue;
0398
0399 if (i == CPUIDLE_STATE_MAX) {
0400 pr_warn("%s: cpuidle states reached max possible\n",
0401 __func__);
0402 break;
0403 }
0404
0405 states[state_count].wfi_flags = 0;
0406
0407 if (of_property_read_bool(state_node, "ti,idle-wkup-m3"))
0408 states[state_count].wfi_flags |= WFI_FLAG_WAKE_M3 |
0409 WFI_FLAG_FLUSH_CACHE;
0410
0411 state_count++;
0412 }
0413
0414 idle_states = kcalloc(state_count, sizeof(*idle_states), GFP_KERNEL);
0415 if (!idle_states)
0416 return -ENOMEM;
0417
0418 for (i = 1; i < state_count; i++)
0419 idle_states[i].wfi_flags = states[i].wfi_flags;
0420
0421 return 0;
0422 }
0423
0424 static int amx3_idle_enter(unsigned long index)
0425 {
0426 struct amx3_idle_state *idle_state = &idle_states[index];
0427
0428 if (!idle_state)
0429 return -EINVAL;
0430
0431 if (idle_fn)
0432 idle_fn(idle_state->wfi_flags);
0433
0434 return 0;
0435 }
0436
0437 static struct cpuidle_ops amx3_cpuidle_ops __initdata = {
0438 .init = amx3_idle_init,
0439 .suspend = amx3_idle_enter,
0440 };
0441
0442 CPUIDLE_METHOD_OF_DECLARE(pm33xx_idle, "ti,am3352", &amx3_cpuidle_ops);
0443 CPUIDLE_METHOD_OF_DECLARE(pm43xx_idle, "ti,am4372", &amx3_cpuidle_ops);