arm/mach-omap2/pm24xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * OMAP2 Power Management Routines
0004  *
0005  * Copyright (C) 2005 Texas Instruments, Inc.
0006  * Copyright (C) 2006-2008 Nokia Corporation
0007  *
0008  * Written by:
0009  * Richard Woodruff <r-woodruff2@ti.com>
0010  * Tony Lindgren
0011  * Juha Yrjola
0012  * Amit Kucheria <amit.kucheria@nokia.com>
0013  * Igor Stoppa <igor.stoppa@nokia.com>
0014  *
0015  * Based on pm.c for omap1
0016  */
0017
0018 #include <linux/cpu_pm.h>
0019 #include <linux/suspend.h>
0020 #include <linux/sched.h>
0021 #include <linux/proc_fs.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/sysfs.h>
0024 #include <linux/module.h>
0025 #include <linux/delay.h>
0026 #include <linux/clk.h>
0027 #include <linux/clk-provider.h>
0028 #include <linux/irq.h>
0029 #include <linux/time.h>
0030
0031 #include <asm/fncpy.h>
0032
0033 #include <asm/mach/time.h>
0034 #include <asm/mach/irq.h>
0035 #include <asm/mach-types.h>
0036 #include <asm/system_misc.h>
0037
0038 #include <linux/omap-dma.h>
0039
0040 #include "soc.h"
0041 #include "common.h"
0042 #include "clock.h"
0043 #include "prm2xxx.h"
0044 #include "prm-regbits-24xx.h"
0045 #include "cm2xxx.h"
0046 #include "cm-regbits-24xx.h"
0047 #include "sdrc.h"
0048 #include "sram.h"
0049 #include "pm.h"
0050 #include "control.h"
0051 #include "powerdomain.h"
0052 #include "clockdomain.h"
0053
0054 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
0055                   void __iomem *sdrc_power);
0056
0057 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
0058 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
0059
0060 static struct clk *osc_ck, *emul_ck;
0061
0062 static int omap2_enter_full_retention(void)
0063 {
0064     u32 l;
0065
0066     /* There is 1 reference hold for all children of the oscillator
0067      * clock, the following will remove it. If no one else uses the
0068      * oscillator itself it will be disabled if/when we enter retention
0069      * mode.
0070      */
0071     clk_disable(osc_ck);
0072
0073     /* Clear old wake-up events */
0074     /* REVISIT: These write to reserved bits? */
0075     omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
0076     omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
0077     omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
0078
0079     pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
0080     pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
0081
0082     /* Workaround to kill USB */
0083     l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
0084     omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
0085
0086     /* One last check for pending IRQs to avoid extra latency due
0087      * to sleeping unnecessarily. */
0088     if (omap_irq_pending())
0089         goto no_sleep;
0090
0091     /* Jump to SRAM suspend code */
0092     omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
0093                OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
0094                OMAP_SDRC_REGADDR(SDRC_POWER));
0095
0096 no_sleep:
0097     clk_enable(osc_ck);
0098
0099     /* clear CORE wake-up events */
0100     omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
0101     omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
0102
0103     /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
0104     omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
0105
0106     /* MPU domain wake events */
0107     omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x1);
0108
0109     omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x20);
0110
0111     pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
0112     pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
0113
0114     return 0;
0115 }
0116
0117 static int sti_console_enabled;
0118
0119 static int omap2_allow_mpu_retention(void)
0120 {
0121     if (!omap2xxx_cm_mpu_retention_allowed())
0122         return 0;
0123     if (sti_console_enabled)
0124         return 0;
0125
0126     return 1;
0127 }
0128
0129 static void omap2_enter_mpu_retention(void)
0130 {
0131     const int zero = 0;
0132
0133     /* The peripherals seem not to be able to wake up the MPU when
0134      * it is in retention mode. */
0135     if (omap2_allow_mpu_retention()) {
0136         /* REVISIT: These write to reserved bits? */
0137         omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
0138         omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
0139         omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
0140
0141         /* Try to enter MPU retention */
0142         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
0143
0144     } else {
0145         /* Block MPU retention */
0146         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
0147     }
0148
0149     /* WFI */
0150     asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc");
0151
0152     pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
0153 }
0154
0155 static int omap2_can_sleep(void)
0156 {
0157     if (omap2xxx_cm_fclks_active())
0158         return 0;
0159     if (__clk_is_enabled(osc_ck))
0160         return 0;
0161
0162     return 1;
0163 }
0164
0165 static void omap2_pm_idle(void)
0166 {
0167     int error;
0168
0169     if (omap_irq_pending())
0170         return;
0171
0172     error = cpu_cluster_pm_enter();
0173     if (error || !omap2_can_sleep()) {
0174         omap2_enter_mpu_retention();
0175         goto out_cpu_cluster_pm;
0176     }
0177
0178     omap2_enter_full_retention();
0179
0180 out_cpu_cluster_pm:
0181     cpu_cluster_pm_exit();
0182 }
0183
0184 static void __init prcm_setup_regs(void)
0185 {
0186     int i, num_mem_banks;
0187     struct powerdomain *pwrdm;
0188
0189     /*
0190      * Enable autoidle
0191      * XXX This should be handled by hwmod code or PRCM init code
0192      */
0193     omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
0194               OMAP2_PRCM_SYSCONFIG_OFFSET);
0195
0196     /*
0197      * Set CORE powerdomain memory banks to retain their contents
0198      * during RETENTION
0199      */
0200     num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
0201     for (i = 0; i < num_mem_banks; i++)
0202         pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
0203
0204     pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET);
0205
0206     pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
0207
0208     /* Force-power down DSP, GFX powerdomains */
0209
0210     pwrdm = clkdm_get_pwrdm(dsp_clkdm);
0211     pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
0212
0213     pwrdm = clkdm_get_pwrdm(gfx_clkdm);
0214     pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
0215
0216     /* Enable hardware-supervised idle for all clkdms */
0217     clkdm_for_each(omap_pm_clkdms_setup, NULL);
0218     clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
0219
0220     omap_common_suspend_init(omap2_enter_full_retention);
0221
0222     /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
0223      * stabilisation */
0224     omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
0225                 OMAP2_PRCM_CLKSSETUP_OFFSET);
0226
0227     /* Configure automatic voltage transition */
0228     omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
0229                 OMAP2_PRCM_VOLTSETUP_OFFSET);
0230     omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
0231                 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
0232                 OMAP24XX_MEMRETCTRL_MASK |
0233                 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
0234                 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
0235                 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
0236
0237     /* Enable wake-up events */
0238     omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
0239                 WKUP_MOD, PM_WKEN);
0240
0241     /* Enable SYS_CLKEN control when all domains idle */
0242     omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD,
0243                    OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
0244 }
0245
0246 int __init omap2_pm_init(void)
0247 {
0248     u32 l;
0249
0250     printk(KERN_INFO "Power Management for OMAP2 initializing\n");
0251     l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
0252     printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
0253
0254     /* Look up important powerdomains */
0255
0256     mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
0257     if (!mpu_pwrdm)
0258         pr_err("PM: mpu_pwrdm not found\n");
0259
0260     core_pwrdm = pwrdm_lookup("core_pwrdm");
0261     if (!core_pwrdm)
0262         pr_err("PM: core_pwrdm not found\n");
0263
0264     /* Look up important clockdomains */
0265
0266     mpu_clkdm = clkdm_lookup("mpu_clkdm");
0267     if (!mpu_clkdm)
0268         pr_err("PM: mpu_clkdm not found\n");
0269
0270     wkup_clkdm = clkdm_lookup("wkup_clkdm");
0271     if (!wkup_clkdm)
0272         pr_err("PM: wkup_clkdm not found\n");
0273
0274     dsp_clkdm = clkdm_lookup("dsp_clkdm");
0275     if (!dsp_clkdm)
0276         pr_err("PM: dsp_clkdm not found\n");
0277
0278     gfx_clkdm = clkdm_lookup("gfx_clkdm");
0279     if (!gfx_clkdm)
0280         pr_err("PM: gfx_clkdm not found\n");
0281
0282
0283     osc_ck = clk_get(NULL, "osc_ck");
0284     if (IS_ERR(osc_ck)) {
0285         printk(KERN_ERR "could not get osc_ck\n");
0286         return -ENODEV;
0287     }
0288
0289     if (cpu_is_omap242x()) {
0290         emul_ck = clk_get(NULL, "emul_ck");
0291         if (IS_ERR(emul_ck)) {
0292             printk(KERN_ERR "could not get emul_ck\n");
0293             clk_put(osc_ck);
0294             return -ENODEV;
0295         }
0296     }
0297
0298     prcm_setup_regs();
0299
0300     /*
0301      * We copy the assembler sleep/wakeup routines to SRAM.
0302      * These routines need to be in SRAM as that's the only
0303      * memory the MPU can see when it wakes up after the entire
0304      * chip enters idle.
0305      */
0306     omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
0307                         omap24xx_cpu_suspend_sz);
0308
0309     arm_pm_idle = omap2_pm_idle;
0310
0311     return 0;
0312 }