arm/mach-omap2/opp2430_data.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * opp2430_data.c - old-style "OPP" table for OMAP2430
0004  *
0005  * Copyright (C) 2005-2009 Texas Instruments, Inc.
0006  * Copyright (C) 2004-2009 Nokia Corporation
0007  *
0008  * Richard Woodruff <r-woodruff2@ti.com>
0009  *
0010  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
0011  * These configurations are characterized by voltage and speed for clocks.
0012  * The device is only validated for certain combinations. One way to express
0013  * these combinations is via the 'ratios' which the clocks operate with
0014  * respect to each other. These ratio sets are for a given voltage/DPLL
0015  * setting. All configurations can be described by a DPLL setting and a ratio.
0016  *
0017  * 2430 differs from 2420 in that there are no more phase synchronizers used.
0018  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
0019  * 2430 (iva2.1, NOdsp, mdm)
0020  *
0021  * XXX Missing voltage data.
0022  * XXX Missing 19.2MHz sys_clk rate sets.
0023  *
0024  * THe format described in this file is deprecated.  Once a reasonable
0025  * OPP API exists, the data in this file should be converted to use it.
0026  *
0027  * This is technically part of the OMAP2xxx clock code.
0028  */
0029
0030 #include <linux/kernel.h>
0031
0032 #include "opp2xxx.h"
0033 #include "sdrc.h"
0034 #include "clock.h"
0035
0036 /*
0037  * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
0038  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
0039  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
0040  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
0041  *
0042  * Filling in table based on 2430-SDPs variants available.  There are
0043  * quite a few more rate combinations which could be defined.
0044  *
0045  * When multiple values are defined the start up will try and choose
0046  * the fastest one. If a 'fast' value is defined, then automatically,
0047  * the /2 one should be included as it can be used.  Generally having
0048  * more than one fast set does not make sense, as static timings need
0049  * to be changed to change the set.  The exception is the bypass
0050  * setting which is available for low power bypass.
0051  *
0052  * Note: This table needs to be sorted, fastest to slowest.
0053  */
0054 const struct prcm_config omap2430_rate_table[] = {
0055     /* PRCM #4 - ratio2 (ES2.1) - FAST */
0056     {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,      /* 399MHz ARM */
0057         R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
0058         R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
0059         MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
0060         SDRC_RFR_CTRL_133MHz,
0061         RATE_IN_243X},
0062
0063     /* PRCM #2 - ratio1 (ES2) - FAST */
0064     {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,      /* 330MHz ARM */
0065         R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
0066         R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
0067         MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
0068         SDRC_RFR_CTRL_165MHz,
0069         RATE_IN_243X},
0070
0071     /* PRCM #5a - ratio1 - FAST */
0072     {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,      /* 266MHz ARM */
0073         R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
0074         R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
0075         MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
0076         SDRC_RFR_CTRL_133MHz,
0077         RATE_IN_243X},
0078
0079     /* PRCM #5b - ratio1 - FAST */
0080     {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,      /* 200MHz ARM */
0081         R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
0082         R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
0083         MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
0084         SDRC_RFR_CTRL_100MHz,
0085         RATE_IN_243X},
0086
0087     /* PRCM #4 - ratio1 (ES2.1) - SLOW */
0088     {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,      /* 200MHz ARM */
0089         R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
0090         R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
0091         MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
0092         SDRC_RFR_CTRL_133MHz,
0093         RATE_IN_243X},
0094
0095     /* PRCM #2 - ratio1 (ES2) - SLOW */
0096     {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,      /* 165MHz ARM */
0097         R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
0098         R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
0099         MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
0100         SDRC_RFR_CTRL_165MHz,
0101         RATE_IN_243X},
0102
0103     /* PRCM #5a - ratio1 - SLOW */
0104     {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,      /* 133MHz ARM */
0105         R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
0106         R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
0107         MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
0108         SDRC_RFR_CTRL_133MHz,
0109         RATE_IN_243X},
0110
0111     /* PRCM #5b - ratio1 - SLOW*/
0112     {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,      /* 100MHz ARM */
0113         R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
0114         R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
0115         MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
0116         SDRC_RFR_CTRL_100MHz,
0117         RATE_IN_243X},
0118
0119     /* PRCM-boot/bypass */
0120     {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,        /* 13MHz */
0121         RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
0122         RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
0123         MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
0124         SDRC_RFR_CTRL_BYPASS,
0125         RATE_IN_243X},
0126
0127     /* PRCM-boot/bypass */
0128     {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,        /* 12MHz */
0129         RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
0130         RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
0131         MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
0132         SDRC_RFR_CTRL_BYPASS,
0133         RATE_IN_243X},
0134
0135     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
0136 };