arm/mach-omap2/opp2420_data.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * opp2420_data.c - old-style "OPP" table for OMAP2420
0004  *
0005  * Copyright (C) 2005-2009 Texas Instruments, Inc.
0006  * Copyright (C) 2004-2009 Nokia Corporation
0007  *
0008  * Richard Woodruff <r-woodruff2@ti.com>
0009  *
0010  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
0011  * These configurations are characterized by voltage and speed for clocks.
0012  * The device is only validated for certain combinations. One way to express
0013  * these combinations is via the 'ratios' which the clocks operate with
0014  * respect to each other. These ratio sets are for a given voltage/DPLL
0015  * setting. All configurations can be described by a DPLL setting and a ratio.
0016  *
0017  * XXX Missing voltage data.
0018  * XXX Missing 19.2MHz sys_clk rate sets (needed for N800/N810)
0019  *
0020  * THe format described in this file is deprecated.  Once a reasonable
0021  * OPP API exists, the data in this file should be converted to use it.
0022  *
0023  * This is technically part of the OMAP2xxx clock code.
0024  *
0025  * Considerable work is still needed to fully support dynamic frequency
0026  * changes on OMAP2xxx-series chips.  Readers interested in such a
0027  * project are encouraged to review the Maemo Diablo RX-34 and RX-44
0028  * kernel source at:
0029  *     http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
0030  */
0031
0032 #include <linux/kernel.h>
0033
0034 #include "opp2xxx.h"
0035 #include "sdrc.h"
0036 #include "clock.h"
0037
0038 /*
0039  * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
0040  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
0041  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
0042  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
0043  *
0044  * Filling in table based on H4 boards available.  There are quite a
0045  * few more rate combinations which could be defined.
0046  *
0047  * When multiple values are defined the start up will try and choose
0048  * the fastest one. If a 'fast' value is defined, then automatically,
0049  * the /2 one should be included as it can be used.  Generally having
0050  * more than one fast set does not make sense, as static timings need
0051  * to be changed to change the set.  The exception is the bypass
0052  * setting which is available for low power bypass.
0053  *
0054  * Note: This table needs to be sorted, fastest to slowest.
0055  **/
0056 const struct prcm_config omap2420_rate_table[] = {
0057     /* PRCM I - FAST */
0058     {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,      /* 330MHz ARM */
0059         RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
0060         RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
0061         MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
0062         RATE_IN_242X},
0063
0064     /* PRCM II - FAST */
0065     {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,     /* 300MHz ARM */
0066         RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
0067         RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
0068         MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
0069         RATE_IN_242X},
0070
0071     {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,     /* 300MHz ARM */
0072         RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
0073         RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
0074         MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
0075         RATE_IN_242X},
0076
0077     /* PRCM III - FAST */
0078     {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,        /* 266MHz ARM */
0079         RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
0080         RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
0081         MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
0082         RATE_IN_242X},
0083
0084     {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,        /* 266MHz ARM */
0085         RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
0086         RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
0087         MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
0088         RATE_IN_242X},
0089
0090     /* PRCM II - SLOW */
0091     {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,     /* 150MHz ARM */
0092         RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
0093         RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
0094         MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
0095         RATE_IN_242X},
0096
0097     {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,     /* 150MHz ARM */
0098         RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
0099         RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
0100         MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
0101         RATE_IN_242X},
0102
0103     /* PRCM III - SLOW */
0104     {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,        /* 133MHz ARM */
0105         RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
0106         RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
0107         MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
0108         RATE_IN_242X},
0109
0110     {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,        /* 133MHz ARM */
0111         RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
0112         RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
0113         MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
0114         RATE_IN_242X},
0115
0116     /* PRCM-VII (boot-bypass) */
0117     {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,      /* 12MHz ARM*/
0118         RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
0119         RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
0120         MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
0121         RATE_IN_242X},
0122
0123     /* PRCM-VII (boot-bypass) */
0124     {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,      /* 13MHz ARM */
0125         RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
0126         RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
0127         MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
0128         RATE_IN_242X},
0129
0130     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
0131 };