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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
0004  *
0005  * Copyright (C) 2009-2011 Nokia Corporation
0006  * Copyright (C) 2012 Texas Instruments, Inc.
0007  * Paul Walmsley
0008  *
0009  * XXX handle crossbar/shared link difference for L3?
0010  * XXX these should be marked initdata for multi-OMAP kernels
0011  */
0012 
0013 #include <linux/platform_data/i2c-omap.h>
0014 #include <linux/platform_data/hsmmc-omap.h>
0015 
0016 #include "omap_hwmod.h"
0017 #include "l3_2xxx.h"
0018 
0019 #include "soc.h"
0020 #include "omap_hwmod_common_data.h"
0021 #include "prm-regbits-24xx.h"
0022 #include "cm-regbits-24xx.h"
0023 #include "i2c.h"
0024 #include "wd_timer.h"
0025 
0026 /*
0027  * OMAP2430 hardware module integration data
0028  *
0029  * All of the data in this section should be autogeneratable from the
0030  * TI hardware database or other technical documentation.  Data that
0031  * is driver-specific or driver-kernel integration-specific belongs
0032  * elsewhere.
0033  */
0034 
0035 /*
0036  * IP blocks
0037  */
0038 
0039 /* IVA2 (IVA2) */
0040 static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
0041     { .name = "logic", .rst_shift = 0 },
0042     { .name = "mmu", .rst_shift = 1 },
0043 };
0044 
0045 static struct omap_hwmod omap2430_iva_hwmod = {
0046     .name       = "iva",
0047     .class      = &iva_hwmod_class,
0048     .clkdm_name = "dsp_clkdm",
0049     .rst_lines  = omap2430_iva_resets,
0050     .rst_lines_cnt  = ARRAY_SIZE(omap2430_iva_resets),
0051     .main_clk   = "dsp_fck",
0052 };
0053 
0054 /* I2C common */
0055 static struct omap_hwmod_class_sysconfig i2c_sysc = {
0056     .rev_offs   = 0x00,
0057     .sysc_offs  = 0x20,
0058     .syss_offs  = 0x10,
0059     .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
0060                SYSS_HAS_RESET_STATUS),
0061     .sysc_fields    = &omap_hwmod_sysc_type1,
0062 };
0063 
0064 static struct omap_hwmod_class i2c_class = {
0065     .name       = "i2c",
0066     .sysc       = &i2c_sysc,
0067     .reset      = &omap_i2c_reset,
0068 };
0069 
0070 /* I2C1 */
0071 static struct omap_hwmod omap2430_i2c1_hwmod = {
0072     .name       = "i2c1",
0073     .flags      = HWMOD_16BIT_REG,
0074     .main_clk   = "i2chs1_fck",
0075     .prcm       = {
0076         .omap2 = {
0077             /*
0078              * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
0079              * I2CHS IP's do not follow the usual pattern.
0080              * prcm_reg_id alone cannot be used to program
0081              * the iclk and fclk. Needs to be handled using
0082              * additional flags when clk handling is moved
0083              * to hwmod framework.
0084              */
0085             .module_offs = CORE_MOD,
0086             .idlest_reg_id = 1,
0087             .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
0088         },
0089     },
0090     .class      = &i2c_class,
0091 };
0092 
0093 /* I2C2 */
0094 static struct omap_hwmod omap2430_i2c2_hwmod = {
0095     .name       = "i2c2",
0096     .flags      = HWMOD_16BIT_REG,
0097     .main_clk   = "i2chs2_fck",
0098     .prcm       = {
0099         .omap2 = {
0100             .module_offs = CORE_MOD,
0101             .idlest_reg_id = 1,
0102             .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
0103         },
0104     },
0105     .class      = &i2c_class,
0106 };
0107 
0108 /* gpio5 */
0109 static struct omap_hwmod omap2430_gpio5_hwmod = {
0110     .name       = "gpio5",
0111     .flags      = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
0112     .main_clk   = "gpio5_fck",
0113     .prcm       = {
0114         .omap2 = {
0115             .module_offs = CORE_MOD,
0116             .idlest_reg_id = 2,
0117             .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
0118         },
0119     },
0120     .class      = &omap2xxx_gpio_hwmod_class,
0121 };
0122 
0123 /* mailbox */
0124 static struct omap_hwmod omap2430_mailbox_hwmod = {
0125     .name       = "mailbox",
0126     .class      = &omap2xxx_mailbox_hwmod_class,
0127     .main_clk   = "mailboxes_ick",
0128     .prcm       = {
0129         .omap2 = {
0130             .module_offs = CORE_MOD,
0131             .idlest_reg_id = 1,
0132             .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
0133         },
0134     },
0135 };
0136 
0137 /* mcspi3 */
0138 static struct omap_hwmod omap2430_mcspi3_hwmod = {
0139     .name       = "mcspi3",
0140     .main_clk   = "mcspi3_fck",
0141     .prcm       = {
0142         .omap2 = {
0143             .module_offs = CORE_MOD,
0144             .idlest_reg_id = 2,
0145             .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
0146         },
0147     },
0148     .class      = &omap2xxx_mcspi_class,
0149 };
0150 
0151 /* usbhsotg */
0152 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
0153     .rev_offs   = 0x0400,
0154     .sysc_offs  = 0x0404,
0155     .syss_offs  = 0x0408,
0156     .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
0157               SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
0158               SYSC_HAS_AUTOIDLE),
0159     .idlemodes  = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
0160               MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
0161     .sysc_fields    = &omap_hwmod_sysc_type1,
0162 };
0163 
0164 static struct omap_hwmod_class usbotg_class = {
0165     .name = "usbotg",
0166     .sysc = &omap2430_usbhsotg_sysc,
0167 };
0168 
0169 /* usb_otg_hs */
0170 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
0171     .name       = "usb_otg_hs",
0172     .main_clk   = "usbhs_ick",
0173     .prcm       = {
0174         .omap2 = {
0175             .module_offs = CORE_MOD,
0176             .idlest_reg_id = 1,
0177             .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
0178         },
0179     },
0180     .class      = &usbotg_class,
0181     /*
0182      * Erratum ID: i479  idle_req / idle_ack mechanism potentially
0183      * broken when autoidle is enabled
0184      * workaround is to disable the autoidle bit at module level.
0185      */
0186     .flags      = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
0187                 | HWMOD_SWSUP_MSTANDBY,
0188 };
0189 
0190 /*
0191  * 'mcbsp' class
0192  * multi channel buffered serial port controller
0193  */
0194 
0195 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
0196     .rev_offs   = 0x007C,
0197     .sysc_offs  = 0x008C,
0198     .sysc_flags = (SYSC_HAS_SOFTRESET),
0199     .sysc_fields    = &omap_hwmod_sysc_type1,
0200 };
0201 
0202 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
0203     .name = "mcbsp",
0204     .sysc = &omap2430_mcbsp_sysc,
0205 };
0206 
0207 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
0208     { .role = "pad_fck", .clk = "mcbsp_clks" },
0209     { .role = "prcm_fck", .clk = "func_96m_ck" },
0210 };
0211 
0212 /* mcbsp1 */
0213 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
0214     .name       = "mcbsp1",
0215     .class      = &omap2430_mcbsp_hwmod_class,
0216     .main_clk   = "mcbsp1_fck",
0217     .prcm       = {
0218         .omap2 = {
0219             .module_offs = CORE_MOD,
0220             .idlest_reg_id = 1,
0221             .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
0222         },
0223     },
0224     .opt_clks   = mcbsp_opt_clks,
0225     .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
0226 };
0227 
0228 /* mcbsp2 */
0229 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
0230     .name       = "mcbsp2",
0231     .class      = &omap2430_mcbsp_hwmod_class,
0232     .main_clk   = "mcbsp2_fck",
0233     .prcm       = {
0234         .omap2 = {
0235             .module_offs = CORE_MOD,
0236             .idlest_reg_id = 1,
0237             .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
0238         },
0239     },
0240     .opt_clks   = mcbsp_opt_clks,
0241     .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
0242 };
0243 
0244 /* mcbsp3 */
0245 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
0246     .name       = "mcbsp3",
0247     .class      = &omap2430_mcbsp_hwmod_class,
0248     .main_clk   = "mcbsp3_fck",
0249     .prcm       = {
0250         .omap2 = {
0251             .module_offs = CORE_MOD,
0252             .idlest_reg_id = 2,
0253             .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
0254         },
0255     },
0256     .opt_clks   = mcbsp_opt_clks,
0257     .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
0258 };
0259 
0260 /* mcbsp4 */
0261 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
0262     .name       = "mcbsp4",
0263     .class      = &omap2430_mcbsp_hwmod_class,
0264     .main_clk   = "mcbsp4_fck",
0265     .prcm       = {
0266         .omap2 = {
0267             .module_offs = CORE_MOD,
0268             .idlest_reg_id = 2,
0269             .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
0270         },
0271     },
0272     .opt_clks   = mcbsp_opt_clks,
0273     .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
0274 };
0275 
0276 /* mcbsp5 */
0277 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
0278     .name       = "mcbsp5",
0279     .class      = &omap2430_mcbsp_hwmod_class,
0280     .main_clk   = "mcbsp5_fck",
0281     .prcm       = {
0282         .omap2 = {
0283             .module_offs = CORE_MOD,
0284             .idlest_reg_id = 2,
0285             .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
0286         },
0287     },
0288     .opt_clks   = mcbsp_opt_clks,
0289     .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
0290 };
0291 
0292 /* MMC/SD/SDIO common */
0293 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
0294     .rev_offs   = 0x1fc,
0295     .sysc_offs  = 0x10,
0296     .syss_offs  = 0x14,
0297     .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
0298                SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
0299                SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
0300     .idlemodes  = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
0301     .sysc_fields    = &omap_hwmod_sysc_type1,
0302 };
0303 
0304 static struct omap_hwmod_class omap2430_mmc_class = {
0305     .name = "mmc",
0306     .sysc = &omap2430_mmc_sysc,
0307 };
0308 
0309 /* MMC/SD/SDIO1 */
0310 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
0311     { .role = "dbck", .clk = "mmchsdb1_fck" },
0312 };
0313 
0314 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
0315     .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
0316 };
0317 
0318 static struct omap_hwmod omap2430_mmc1_hwmod = {
0319     .name       = "mmc1",
0320     .flags      = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
0321     .opt_clks   = omap2430_mmc1_opt_clks,
0322     .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
0323     .main_clk   = "mmchs1_fck",
0324     .prcm       = {
0325         .omap2 = {
0326             .module_offs = CORE_MOD,
0327             .idlest_reg_id = 2,
0328             .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
0329         },
0330     },
0331     .dev_attr   = &mmc1_dev_attr,
0332     .class      = &omap2430_mmc_class,
0333 };
0334 
0335 /* MMC/SD/SDIO2 */
0336 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
0337     { .role = "dbck", .clk = "mmchsdb2_fck" },
0338 };
0339 
0340 static struct omap_hwmod omap2430_mmc2_hwmod = {
0341     .name       = "mmc2",
0342     .flags      = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
0343     .opt_clks   = omap2430_mmc2_opt_clks,
0344     .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
0345     .main_clk   = "mmchs2_fck",
0346     .prcm       = {
0347         .omap2 = {
0348             .module_offs = CORE_MOD,
0349             .idlest_reg_id = 2,
0350             .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
0351         },
0352     },
0353     .class      = &omap2430_mmc_class,
0354 };
0355 
0356 /* HDQ1W/1-wire */
0357 static struct omap_hwmod omap2430_hdq1w_hwmod = {
0358     .name       = "hdq1w",
0359     .main_clk   = "hdq_fck",
0360     .prcm       = {
0361         .omap2 = {
0362             .module_offs = CORE_MOD,
0363             .idlest_reg_id = 1,
0364             .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
0365         },
0366     },
0367     .class      = &omap2_hdq1w_class,
0368 };
0369 
0370 /*
0371  * interfaces
0372  */
0373 
0374 /* L3 -> L4_CORE interface */
0375 /* l3_core -> usbhsotg  interface */
0376 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
0377     .master     = &omap2430_usbhsotg_hwmod,
0378     .slave      = &omap2xxx_l3_main_hwmod,
0379     .clk        = "core_l3_ck",
0380     .user       = OCP_USER_MPU,
0381 };
0382 
0383 /* L4 CORE -> I2C1 interface */
0384 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
0385     .master     = &omap2xxx_l4_core_hwmod,
0386     .slave      = &omap2430_i2c1_hwmod,
0387     .clk        = "i2c1_ick",
0388     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0389 };
0390 
0391 /* L4 CORE -> I2C2 interface */
0392 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
0393     .master     = &omap2xxx_l4_core_hwmod,
0394     .slave      = &omap2430_i2c2_hwmod,
0395     .clk        = "i2c2_ick",
0396     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0397 };
0398 
0399 /*  l4_core ->usbhsotg  interface */
0400 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
0401     .master     = &omap2xxx_l4_core_hwmod,
0402     .slave      = &omap2430_usbhsotg_hwmod,
0403     .clk        = "usb_l4_ick",
0404     .user       = OCP_USER_MPU,
0405 };
0406 
0407 /* L4 CORE -> MMC1 interface */
0408 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
0409     .master     = &omap2xxx_l4_core_hwmod,
0410     .slave      = &omap2430_mmc1_hwmod,
0411     .clk        = "mmchs1_ick",
0412     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0413 };
0414 
0415 /* L4 CORE -> MMC2 interface */
0416 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
0417     .master     = &omap2xxx_l4_core_hwmod,
0418     .slave      = &omap2430_mmc2_hwmod,
0419     .clk        = "mmchs2_ick",
0420     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0421 };
0422 
0423 /* l4 core -> mcspi3 interface */
0424 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
0425     .master     = &omap2xxx_l4_core_hwmod,
0426     .slave      = &omap2430_mcspi3_hwmod,
0427     .clk        = "mcspi3_ick",
0428     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0429 };
0430 
0431 /* IVA2 <- L3 interface */
0432 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
0433     .master     = &omap2xxx_l3_main_hwmod,
0434     .slave      = &omap2430_iva_hwmod,
0435     .clk        = "core_l3_ck",
0436     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0437 };
0438 
0439 /* l4_wkup -> wd_timer2 */
0440 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
0441     .master     = &omap2xxx_l4_wkup_hwmod,
0442     .slave      = &omap2xxx_wd_timer2_hwmod,
0443     .clk        = "mpu_wdt_ick",
0444     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0445 };
0446 
0447 /* l4_wkup -> gpio1 */
0448 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
0449     .master     = &omap2xxx_l4_wkup_hwmod,
0450     .slave      = &omap2xxx_gpio1_hwmod,
0451     .clk        = "gpios_ick",
0452     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0453 };
0454 
0455 /* l4_wkup -> gpio2 */
0456 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
0457     .master     = &omap2xxx_l4_wkup_hwmod,
0458     .slave      = &omap2xxx_gpio2_hwmod,
0459     .clk        = "gpios_ick",
0460     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0461 };
0462 
0463 /* l4_wkup -> gpio3 */
0464 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
0465     .master     = &omap2xxx_l4_wkup_hwmod,
0466     .slave      = &omap2xxx_gpio3_hwmod,
0467     .clk        = "gpios_ick",
0468     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0469 };
0470 
0471 /* l4_wkup -> gpio4 */
0472 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
0473     .master     = &omap2xxx_l4_wkup_hwmod,
0474     .slave      = &omap2xxx_gpio4_hwmod,
0475     .clk        = "gpios_ick",
0476     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0477 };
0478 
0479 /* l4_core -> gpio5 */
0480 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
0481     .master     = &omap2xxx_l4_core_hwmod,
0482     .slave      = &omap2430_gpio5_hwmod,
0483     .clk        = "gpio5_ick",
0484     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0485 };
0486 
0487 /* l4_core -> mailbox */
0488 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
0489     .master     = &omap2xxx_l4_core_hwmod,
0490     .slave      = &omap2430_mailbox_hwmod,
0491     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0492 };
0493 
0494 /* l4_core -> mcbsp1 */
0495 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
0496     .master     = &omap2xxx_l4_core_hwmod,
0497     .slave      = &omap2430_mcbsp1_hwmod,
0498     .clk        = "mcbsp1_ick",
0499     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0500 };
0501 
0502 /* l4_core -> mcbsp2 */
0503 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
0504     .master     = &omap2xxx_l4_core_hwmod,
0505     .slave      = &omap2430_mcbsp2_hwmod,
0506     .clk        = "mcbsp2_ick",
0507     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0508 };
0509 
0510 /* l4_core -> mcbsp3 */
0511 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
0512     .master     = &omap2xxx_l4_core_hwmod,
0513     .slave      = &omap2430_mcbsp3_hwmod,
0514     .clk        = "mcbsp3_ick",
0515     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0516 };
0517 
0518 /* l4_core -> mcbsp4 */
0519 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
0520     .master     = &omap2xxx_l4_core_hwmod,
0521     .slave      = &omap2430_mcbsp4_hwmod,
0522     .clk        = "mcbsp4_ick",
0523     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0524 };
0525 
0526 /* l4_core -> mcbsp5 */
0527 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
0528     .master     = &omap2xxx_l4_core_hwmod,
0529     .slave      = &omap2430_mcbsp5_hwmod,
0530     .clk        = "mcbsp5_ick",
0531     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0532 };
0533 
0534 /* l4_core -> hdq1w */
0535 static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
0536     .master     = &omap2xxx_l4_core_hwmod,
0537     .slave      = &omap2430_hdq1w_hwmod,
0538     .clk        = "hdq_ick",
0539     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0540     .flags      = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
0541 };
0542 
0543 static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
0544     .master     = &omap2xxx_l3_main_hwmod,
0545     .slave      = &omap2xxx_gpmc_hwmod,
0546     .clk        = "core_l3_ck",
0547     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0548 };
0549 
0550 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
0551     &omap2xxx_l3_main__l4_core,
0552     &omap2xxx_mpu__l3_main,
0553     &omap2xxx_dss__l3,
0554     &omap2430_usbhsotg__l3,
0555     &omap2430_l4_core__i2c1,
0556     &omap2430_l4_core__i2c2,
0557     &omap2xxx_l4_core__l4_wkup,
0558     &omap2_l4_core__uart1,
0559     &omap2_l4_core__uart2,
0560     &omap2_l4_core__uart3,
0561     &omap2430_l4_core__usbhsotg,
0562     &omap2430_l4_core__mmc1,
0563     &omap2430_l4_core__mmc2,
0564     &omap2xxx_l4_core__mcspi1,
0565     &omap2xxx_l4_core__mcspi2,
0566     &omap2430_l4_core__mcspi3,
0567     &omap2430_l3__iva,
0568     &omap2xxx_l4_core__timer3,
0569     &omap2xxx_l4_core__timer4,
0570     &omap2xxx_l4_core__timer5,
0571     &omap2xxx_l4_core__timer6,
0572     &omap2xxx_l4_core__timer7,
0573     &omap2xxx_l4_core__timer8,
0574     &omap2xxx_l4_core__timer9,
0575     &omap2xxx_l4_core__timer10,
0576     &omap2xxx_l4_core__timer11,
0577     &omap2xxx_l4_core__timer12,
0578     &omap2430_l4_wkup__wd_timer2,
0579     &omap2xxx_l4_core__dss,
0580     &omap2xxx_l4_core__dss_dispc,
0581     &omap2xxx_l4_core__dss_rfbi,
0582     &omap2xxx_l4_core__dss_venc,
0583     &omap2430_l4_wkup__gpio1,
0584     &omap2430_l4_wkup__gpio2,
0585     &omap2430_l4_wkup__gpio3,
0586     &omap2430_l4_wkup__gpio4,
0587     &omap2430_l4_core__gpio5,
0588     &omap2430_l4_core__mailbox,
0589     &omap2430_l4_core__mcbsp1,
0590     &omap2430_l4_core__mcbsp2,
0591     &omap2430_l4_core__mcbsp3,
0592     &omap2430_l4_core__mcbsp4,
0593     &omap2430_l4_core__mcbsp5,
0594     &omap2430_l4_core__hdq1w,
0595     &omap2xxx_l4_core__rng,
0596     &omap2xxx_l4_core__sham,
0597     &omap2xxx_l4_core__aes,
0598     &omap2430_l3__gpmc,
0599     NULL,
0600 };
0601 
0602 int __init omap2430_hwmod_init(void)
0603 {
0604     omap_hwmod_init();
0605     return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
0606 }
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