arm/mach-omap2/omap_hwmod_2420_data.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
0004  *
0005  * Copyright (C) 2009-2011 Nokia Corporation
0006  * Copyright (C) 2012 Texas Instruments, Inc.
0007  * Paul Walmsley
0008  *
0009  * XXX handle crossbar/shared link difference for L3?
0010  * XXX these should be marked initdata for multi-OMAP kernels
0011  */
0012
0013 #include <linux/platform_data/i2c-omap.h>
0014
0015 #include "omap_hwmod.h"
0016 #include "l3_2xxx.h"
0017 #include "l4_2xxx.h"
0018
0019 #include "omap_hwmod_common_data.h"
0020
0021 #include "cm-regbits-24xx.h"
0022 #include "prm-regbits-24xx.h"
0023 #include "i2c.h"
0024 #include "mmc.h"
0025 #include "serial.h"
0026 #include "wd_timer.h"
0027
0028 /*
0029  * OMAP2420 hardware module integration data
0030  *
0031  * All of the data in this section should be autogeneratable from the
0032  * TI hardware database or other technical documentation.  Data that
0033  * is driver-specific or driver-kernel integration-specific belongs
0034  * elsewhere.
0035  */
0036
0037 /*
0038  * IP blocks
0039  */
0040
0041 /* IVA1 (IVA1) */
0042 static struct omap_hwmod_class iva1_hwmod_class = {
0043     .name       = "iva1",
0044 };
0045
0046 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
0047     { .name = "iva", .rst_shift = 8 },
0048 };
0049
0050 static struct omap_hwmod omap2420_iva_hwmod = {
0051     .name       = "iva",
0052     .class      = &iva1_hwmod_class,
0053     .clkdm_name = "iva1_clkdm",
0054     .rst_lines  = omap2420_iva_resets,
0055     .rst_lines_cnt  = ARRAY_SIZE(omap2420_iva_resets),
0056     .main_clk   = "iva1_ifck",
0057 };
0058
0059 /* DSP */
0060 static struct omap_hwmod_class dsp_hwmod_class = {
0061     .name       = "dsp",
0062 };
0063
0064 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
0065     { .name = "logic", .rst_shift = 0 },
0066     { .name = "mmu", .rst_shift = 1 },
0067 };
0068
0069 static struct omap_hwmod omap2420_dsp_hwmod = {
0070     .name       = "dsp",
0071     .class      = &dsp_hwmod_class,
0072     .clkdm_name = "dsp_clkdm",
0073     .rst_lines  = omap2420_dsp_resets,
0074     .rst_lines_cnt  = ARRAY_SIZE(omap2420_dsp_resets),
0075     .main_clk   = "dsp_fck",
0076 };
0077
0078 /* I2C common */
0079 static struct omap_hwmod_class_sysconfig i2c_sysc = {
0080     .rev_offs   = 0x00,
0081     .sysc_offs  = 0x20,
0082     .syss_offs  = 0x10,
0083     .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
0084     .sysc_fields    = &omap_hwmod_sysc_type1,
0085 };
0086
0087 static struct omap_hwmod_class i2c_class = {
0088     .name       = "i2c",
0089     .sysc       = &i2c_sysc,
0090     .reset      = &omap_i2c_reset,
0091 };
0092
0093 /* I2C1 */
0094 static struct omap_hwmod omap2420_i2c1_hwmod = {
0095     .name       = "i2c1",
0096     .main_clk   = "i2c1_fck",
0097     .prcm       = {
0098         .omap2 = {
0099             .module_offs = CORE_MOD,
0100             .idlest_reg_id = 1,
0101             .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
0102         },
0103     },
0104     .class      = &i2c_class,
0105     /*
0106      * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
0107      * while a transfer is active seems to cause the I2C block to
0108      * timeout. Why? Good question."
0109      */
0110     .flags      = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
0111 };
0112
0113 /* I2C2 */
0114 static struct omap_hwmod omap2420_i2c2_hwmod = {
0115     .name       = "i2c2",
0116     .main_clk   = "i2c2_fck",
0117     .prcm       = {
0118         .omap2 = {
0119             .module_offs = CORE_MOD,
0120             .idlest_reg_id = 1,
0121             .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
0122         },
0123     },
0124     .class      = &i2c_class,
0125     .flags      = HWMOD_16BIT_REG,
0126 };
0127
0128 /* mailbox */
0129 static struct omap_hwmod omap2420_mailbox_hwmod = {
0130     .name       = "mailbox",
0131     .class      = &omap2xxx_mailbox_hwmod_class,
0132     .main_clk   = "mailboxes_ick",
0133     .prcm       = {
0134         .omap2 = {
0135             .module_offs = CORE_MOD,
0136             .idlest_reg_id = 1,
0137             .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
0138         },
0139     },
0140 };
0141
0142 /*
0143  * 'mcbsp' class
0144  * multi channel buffered serial port controller
0145  */
0146
0147 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
0148     .name = "mcbsp",
0149 };
0150
0151 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
0152     { .role = "pad_fck", .clk = "mcbsp_clks" },
0153     { .role = "prcm_fck", .clk = "func_96m_ck" },
0154 };
0155
0156 /* mcbsp1 */
0157 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
0158     .name       = "mcbsp1",
0159     .class      = &omap2420_mcbsp_hwmod_class,
0160     .main_clk   = "mcbsp1_fck",
0161     .prcm       = {
0162         .omap2 = {
0163             .module_offs = CORE_MOD,
0164             .idlest_reg_id = 1,
0165             .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
0166         },
0167     },
0168     .opt_clks   = mcbsp_opt_clks,
0169     .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
0170 };
0171
0172 /* mcbsp2 */
0173 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
0174     .name       = "mcbsp2",
0175     .class      = &omap2420_mcbsp_hwmod_class,
0176     .main_clk   = "mcbsp2_fck",
0177     .prcm       = {
0178         .omap2 = {
0179             .module_offs = CORE_MOD,
0180             .idlest_reg_id = 1,
0181             .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
0182         },
0183     },
0184     .opt_clks   = mcbsp_opt_clks,
0185     .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
0186 };
0187
0188 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
0189     .rev_offs   = 0x3c,
0190     .sysc_offs  = 0x64,
0191     .syss_offs  = 0x68,
0192     .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
0193     .sysc_fields    = &omap_hwmod_sysc_type1,
0194 };
0195
0196 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
0197     .name   = "msdi",
0198     .sysc   = &omap2420_msdi_sysc,
0199     .reset  = &omap_msdi_reset,
0200 };
0201
0202 /* msdi1 */
0203 static struct omap_hwmod omap2420_msdi1_hwmod = {
0204     .name       = "msdi1",
0205     .class      = &omap2420_msdi_hwmod_class,
0206     .main_clk   = "mmc_fck",
0207     .prcm       = {
0208         .omap2 = {
0209             .module_offs = CORE_MOD,
0210             .idlest_reg_id = 1,
0211             .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
0212         },
0213     },
0214     .flags      = HWMOD_16BIT_REG,
0215 };
0216
0217 /* HDQ1W/1-wire */
0218 static struct omap_hwmod omap2420_hdq1w_hwmod = {
0219     .name       = "hdq1w",
0220     .main_clk   = "hdq_fck",
0221     .prcm       = {
0222         .omap2 = {
0223             .module_offs = CORE_MOD,
0224             .idlest_reg_id = 1,
0225             .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
0226         },
0227     },
0228     .class      = &omap2_hdq1w_class,
0229 };
0230
0231 /*
0232  * interfaces
0233  */
0234
0235 /* L4 CORE -> I2C1 interface */
0236 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
0237     .master     = &omap2xxx_l4_core_hwmod,
0238     .slave      = &omap2420_i2c1_hwmod,
0239     .clk        = "i2c1_ick",
0240     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0241 };
0242
0243 /* L4 CORE -> I2C2 interface */
0244 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
0245     .master     = &omap2xxx_l4_core_hwmod,
0246     .slave      = &omap2420_i2c2_hwmod,
0247     .clk        = "i2c2_ick",
0248     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0249 };
0250
0251 /* IVA <- L3 interface */
0252 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
0253     .master     = &omap2xxx_l3_main_hwmod,
0254     .slave      = &omap2420_iva_hwmod,
0255     .clk        = "core_l3_ck",
0256     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0257 };
0258
0259 /* DSP <- L3 interface */
0260 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
0261     .master     = &omap2xxx_l3_main_hwmod,
0262     .slave      = &omap2420_dsp_hwmod,
0263     .clk        = "dsp_ick",
0264     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0265 };
0266
0267 /* l4_wkup -> wd_timer2 */
0268 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
0269     .master     = &omap2xxx_l4_wkup_hwmod,
0270     .slave      = &omap2xxx_wd_timer2_hwmod,
0271     .clk        = "mpu_wdt_ick",
0272     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0273 };
0274
0275 /* l4_wkup -> gpio1 */
0276 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
0277     .master     = &omap2xxx_l4_wkup_hwmod,
0278     .slave      = &omap2xxx_gpio1_hwmod,
0279     .clk        = "gpios_ick",
0280     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0281 };
0282
0283 /* l4_wkup -> gpio2 */
0284 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
0285     .master     = &omap2xxx_l4_wkup_hwmod,
0286     .slave      = &omap2xxx_gpio2_hwmod,
0287     .clk        = "gpios_ick",
0288     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0289 };
0290
0291 /* l4_wkup -> gpio3 */
0292 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
0293     .master     = &omap2xxx_l4_wkup_hwmod,
0294     .slave      = &omap2xxx_gpio3_hwmod,
0295     .clk        = "gpios_ick",
0296     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0297 };
0298
0299 /* l4_wkup -> gpio4 */
0300 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
0301     .master     = &omap2xxx_l4_wkup_hwmod,
0302     .slave      = &omap2xxx_gpio4_hwmod,
0303     .clk        = "gpios_ick",
0304     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0305 };
0306
0307 /* l4_core -> mailbox */
0308 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
0309     .master     = &omap2xxx_l4_core_hwmod,
0310     .slave      = &omap2420_mailbox_hwmod,
0311     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0312 };
0313
0314 /* l4_core -> mcbsp1 */
0315 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
0316     .master     = &omap2xxx_l4_core_hwmod,
0317     .slave      = &omap2420_mcbsp1_hwmod,
0318     .clk        = "mcbsp1_ick",
0319     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0320 };
0321
0322 /* l4_core -> mcbsp2 */
0323 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
0324     .master     = &omap2xxx_l4_core_hwmod,
0325     .slave      = &omap2420_mcbsp2_hwmod,
0326     .clk        = "mcbsp2_ick",
0327     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0328 };
0329
0330 /* l4_core -> msdi1 */
0331 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
0332     .master     = &omap2xxx_l4_core_hwmod,
0333     .slave      = &omap2420_msdi1_hwmod,
0334     .clk        = "mmc_ick",
0335     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0336 };
0337
0338 /* l4_core -> hdq1w interface */
0339 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
0340     .master     = &omap2xxx_l4_core_hwmod,
0341     .slave      = &omap2420_hdq1w_hwmod,
0342     .clk        = "hdq_ick",
0343     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0344     .flags      = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
0345 };
0346
0347 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
0348     .master     = &omap2xxx_l3_main_hwmod,
0349     .slave      = &omap2xxx_gpmc_hwmod,
0350     .clk        = "core_l3_ck",
0351     .user       = OCP_USER_MPU | OCP_USER_SDMA,
0352 };
0353
0354 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
0355     &omap2xxx_l3_main__l4_core,
0356     &omap2xxx_mpu__l3_main,
0357     &omap2xxx_dss__l3,
0358     &omap2xxx_l4_core__mcspi1,
0359     &omap2xxx_l4_core__mcspi2,
0360     &omap2xxx_l4_core__l4_wkup,
0361     &omap2_l4_core__uart1,
0362     &omap2_l4_core__uart2,
0363     &omap2_l4_core__uart3,
0364     &omap2420_l4_core__i2c1,
0365     &omap2420_l4_core__i2c2,
0366     &omap2420_l3__iva,
0367     &omap2420_l3__dsp,
0368     &omap2xxx_l4_core__timer3,
0369     &omap2xxx_l4_core__timer4,
0370     &omap2xxx_l4_core__timer5,
0371     &omap2xxx_l4_core__timer6,
0372     &omap2xxx_l4_core__timer7,
0373     &omap2xxx_l4_core__timer8,
0374     &omap2xxx_l4_core__timer9,
0375     &omap2xxx_l4_core__timer10,
0376     &omap2xxx_l4_core__timer11,
0377     &omap2xxx_l4_core__timer12,
0378     &omap2420_l4_wkup__wd_timer2,
0379     &omap2xxx_l4_core__dss,
0380     &omap2xxx_l4_core__dss_dispc,
0381     &omap2xxx_l4_core__dss_rfbi,
0382     &omap2xxx_l4_core__dss_venc,
0383     &omap2420_l4_wkup__gpio1,
0384     &omap2420_l4_wkup__gpio2,
0385     &omap2420_l4_wkup__gpio3,
0386     &omap2420_l4_wkup__gpio4,
0387     &omap2420_l4_core__mailbox,
0388     &omap2420_l4_core__mcbsp1,
0389     &omap2420_l4_core__mcbsp2,
0390     &omap2420_l4_core__msdi1,
0391     &omap2xxx_l4_core__rng,
0392     &omap2xxx_l4_core__sham,
0393     &omap2xxx_l4_core__aes,
0394     &omap2420_l4_core__hdq1w,
0395     &omap2420_l3__gpmc,
0396     NULL,
0397 };
0398
0399 int __init omap2420_hwmod_init(void)
0400 {
0401     omap_hwmod_init();
0402     return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
0403 }