arm/mach-omap2/omap4-sar-layout.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * omap4-sar-layout.h: OMAP4 SAR RAM layout header file
0004  *
0005  * Copyright (C) 2011 Texas Instruments, Inc.
0006  *  Santosh Shilimkar <santosh.shilimkar@ti.com>
0007  */
0008 #ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H
0009 #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
0010
0011 /*
0012  * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
0013  */
0014 #define SAR_BANK1_OFFSET        0x0000
0015 #define SAR_BANK2_OFFSET        0x1000
0016 #define SAR_BANK3_OFFSET        0x2000
0017 #define SAR_BANK4_OFFSET        0x3000
0018
0019 /* Scratch pad memory offsets from SAR_BANK1 */
0020 #define SCU_OFFSET0             0xfe4
0021 #define SCU_OFFSET1             0xfe8
0022 #define OMAP_TYPE_OFFSET            0xfec
0023 #define L2X0_SAVE_OFFSET0           0xff0
0024 #define L2X0_SAVE_OFFSET1           0xff4
0025 #define L2X0_AUXCTRL_OFFSET         0xff8
0026 #define L2X0_PREFETCH_CTRL_OFFSET       0xffc
0027
0028 /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK1 */
0029 #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET       0xa04
0030 #define CPU1_WAKEUP_NS_PA_ADDR_OFFSET       0xa08
0031 #define OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xe00
0032 #define OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xe04
0033
0034 #define SAR_BACKUP_STATUS_OFFSET        (SAR_BANK3_OFFSET + 0x500)
0035 #define SAR_SECURE_RAM_SIZE_OFFSET      (SAR_BANK3_OFFSET + 0x504)
0036 #define SAR_SECRAM_SAVED_AT_OFFSET      (SAR_BANK3_OFFSET + 0x508)
0037
0038 /* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */
0039 #define WAKEUPGENENB_OFFSET_CPU0        (SAR_BANK3_OFFSET + 0x684)
0040 #define WAKEUPGENENB_SECURE_OFFSET_CPU0     (SAR_BANK3_OFFSET + 0x694)
0041 #define WAKEUPGENENB_OFFSET_CPU1        (SAR_BANK3_OFFSET + 0x6a4)
0042 #define WAKEUPGENENB_SECURE_OFFSET_CPU1     (SAR_BANK3_OFFSET + 0x6b4)
0043 #define AUXCOREBOOT0_OFFSET         (SAR_BANK3_OFFSET + 0x6c4)
0044 #define AUXCOREBOOT1_OFFSET         (SAR_BANK3_OFFSET + 0x6c8)
0045 #define PTMSYNCREQ_MASK_OFFSET          (SAR_BANK3_OFFSET + 0x6cc)
0046 #define PTMSYNCREQ_EN_OFFSET            (SAR_BANK3_OFFSET + 0x6d0)
0047 #define SAR_BACKUP_STATUS_WAKEUPGEN     0x10
0048
0049 /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
0050 #define OMAP5_WAKEUPGENENB_OFFSET_CPU0      (SAR_BANK3_OFFSET + 0x9dc)
0051 #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0   (SAR_BANK3_OFFSET + 0x9f0)
0052 #define OMAP5_WAKEUPGENENB_OFFSET_CPU1      (SAR_BANK3_OFFSET + 0xa04)
0053 #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1   (SAR_BANK3_OFFSET + 0xa18)
0054 #define OMAP5_AUXCOREBOOT0_OFFSET       (SAR_BANK3_OFFSET + 0xa2c)
0055 #define OMAP5_AUXCOREBOOT1_OFFSET       (SAR_BANK3_OFFSET + 0x930)
0056 #define OMAP5_AMBA_IF_MODE_OFFSET       (SAR_BANK3_OFFSET + 0xa34)
0057 #define OMAP5_SAR_BACKUP_STATUS_OFFSET      (SAR_BANK3_OFFSET + 0x800)
0058
0059 #endif