arm/mach-omap2/omap-secure.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * omap-secure.h: OMAP Secure infrastructure header.
0004  *
0005  * Copyright (C) 2011 Texas Instruments, Inc.
0006  *  Santosh Shilimkar <santosh.shilimkar@ti.com>
0007  * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
0008  * Copyright (C) 2013 Pali Rohár <pali@kernel.org>
0009  */
0010 #ifndef OMAP_ARCH_OMAP_SECURE_H
0011 #define OMAP_ARCH_OMAP_SECURE_H
0012
0013 #include <linux/types.h>
0014
0015 /* Monitor error code */
0016 #define  API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR    0xFFFFFFFE
0017 #define  API_HAL_RET_VALUE_SERVICE_UNKNWON      0xFFFFFFFF
0018
0019 /* HAL API error codes */
0020 #define  API_HAL_RET_VALUE_OK       0x00
0021 #define  API_HAL_RET_VALUE_FAIL     0x01
0022
0023 /* Secure HAL API flags */
0024 #define FLAG_START_CRITICAL     0x4
0025 #define FLAG_IRQFIQ_MASK        0x3
0026 #define FLAG_IRQ_ENABLE         0x2
0027 #define FLAG_FIQ_ENABLE         0x1
0028 #define NO_FLAG             0x0
0029
0030 /* Maximum Secure memory storage size */
0031 #define OMAP_SECURE_RAM_STORAGE (88 * SZ_1K)
0032
0033 #define OMAP3_SAVE_SECURE_RAM_SZ    0x803F
0034
0035 /* Secure low power HAL API index */
0036 #define OMAP4_HAL_SAVESECURERAM_INDEX   0x1a
0037 #define OMAP4_HAL_SAVEHW_INDEX      0x1b
0038 #define OMAP4_HAL_SAVEALL_INDEX     0x1c
0039 #define OMAP4_HAL_SAVEGIC_INDEX     0x1d
0040
0041 /* Secure Monitor mode APIs */
0042 #define OMAP4_MON_SCU_PWR_INDEX     0x108
0043 #define OMAP4_MON_L2X0_DBG_CTRL_INDEX   0x100
0044 #define OMAP4_MON_L2X0_CTRL_INDEX   0x102
0045 #define OMAP4_MON_L2X0_AUXCTRL_INDEX    0x109
0046 #define OMAP4_MON_L2X0_PREFETCH_INDEX   0x113
0047
0048 #define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
0049 #define OMAP5_MON_AMBA_IF_INDEX     0x108
0050 #define OMAP5_DRA7_MON_SET_ACR_INDEX    0x107
0051
0052 /* Secure PPA(Primary Protected Application) APIs */
0053 #define OMAP4_PPA_SERVICE_0     0x21
0054 #define OMAP4_PPA_L2_POR_INDEX      0x23
0055 #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX   0x25
0056
0057 #define AM43xx_PPA_SVC_PM_SUSPEND   0x71
0058 #define AM43xx_PPA_SVC_PM_RESUME    0x72
0059
0060 /* Secure RX-51 PPA (Primary Protected Application) APIs */
0061 #define RX51_PPA_HWRNG          29
0062 #define RX51_PPA_L2_INVAL       40
0063 #define RX51_PPA_WRITE_ACR      42
0064
0065 #ifndef __ASSEMBLER__
0066
0067 extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
0068                 u32 arg1, u32 arg2, u32 arg3, u32 arg4);
0069 extern void omap_smccc_smc(u32 fn, u32 arg);
0070 extern void omap_smc1(u32 fn, u32 arg);
0071 extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
0072 extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs);
0073 extern phys_addr_t omap_secure_ram_mempool_base(void);
0074 extern int omap_secure_ram_reserve_memblock(void);
0075 extern u32 save_secure_ram_context(u32 args_pa);
0076 extern u32 omap3_save_secure_ram(void *save_regs, int size);
0077
0078 extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
0079                   u32 arg1, u32 arg2, u32 arg3, u32 arg4);
0080 extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
0081 extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
0082
0083 extern bool optee_available;
0084 void omap_secure_init(void);
0085
0086 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
0087 void set_cntfreq(void);
0088 #else
0089 static inline void set_cntfreq(void)
0090 {
0091 }
0092 #endif
0093
0094 #endif /* __ASSEMBLER__ */
0095 #endif /* OMAP_ARCH_OMAP_SECURE_H */